AD8051AR Analog Devices Inc, AD8051AR Datasheet - Page 16

• Manufacturer Part Number: AD8051AR
• Description: IC OPAMP VF R-R LDIST LP 8SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD8051AR

• Slew Rate: 170 V/µs
• Rohs Status: RoHS non-compliant
• Amplifier Type: Voltage Feedback
• Number Of Circuits: 1
• Output Type: Rail-to-Rail
• -3db Bandwidth: 110MHz
• Current - Input Bias: 1.4µA
• Voltage - Input Offset: 1800µV
• Current - Supply: 4.8mA
• Current - Output / Channel: 45mA
• Voltage - Supply, Single/dual (±): 3 V ~ 12 V, ±1.5 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• No. Of Amplifiers: 1
• Bandwidth: 110MHz
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Gain Bandwidth Product: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD8051/AD8052/AD8054
THEORY OF OPERATION
CIRCUIT DESCRIPTION
The AD8051/AD8052/AD8054 are fabricated on the Analog
Devices, Inc. proprietary eXtra-Fast Complementary Bipolar
(XFCB) process, which enables the construction of PNP and
NPN transistors with similar fTs in the 2 GHz to 4 GHz region.
The process is dielectrically isolated to eliminate the parasitic
and latch-up problems caused by junction isolation. These
features allow the construction of high frequency, low distortion
amplifiers with low supply currents. This design uses a differential
output input stage to maximize bandwidth and headroom (see
Figure 40). The smaller signal swings required on the first stage
outputs (nodes SIP, SIN) reduce the effect of nonlinear currents
due to junction capacitances and improve the distortion per-
formance. This design achieves harmonic distortion of −80 dBc
@ 1 MHz into 100 Ω with V
single 5 V supply.
OUT
= 2 V p-p (gain = +1) on a
V
V
V
V
IN
IN
CC
EE
N
P
Q13
R15 R2
C7
Q1
R26
Figure 40. AD8051/AD8052 Simplified Schematic
Q4
Q2
R5
Q40
SIP
V
I10
EE
Q5
Q3
R21
R39
SIN
Rev. J | Page 16 of 24
Q11
I2
R3
Q22
I3
Q7
Q24
Q25
I7
Q51
Q21
The inputs of the device can handle voltages from −0.2 V below
the negative rail to within 1 V of the positive rail. Exceeding
these values do not cause phase reversal; however, the input
ESD devices begin to conduct if the input voltages exceed the
rails by greater than 0.5 V. During this overdrive condition, the
output stays at the rail.
The rail-to-rail output range of the AD8051/AD8052/AD8054
is provided by a complementary common emitter output stage.
High output drive capability is provided by injecting all output
stage predriver currents directly into the bases of the output
devices Q8 and Q36. Biasing of Q8 and Q36 is accomplished by
I8 and I5, along with a common-mode feedback loop (not
shown). This circuit topology allows the AD8051/AD8052 to
drive 45 mA of output current and allows the AD8054 to drive
30 mA of output current with the outputs within 0.5 V of the
supply rails.
R23 R27
Q27
Q39
Q47
Q50
Q31
I11
Q23
I9
V
V
C9
C3
CC
EE
I8
I5
Q36
Q8
V
OUT