LT1819CS8 Linear Technology, LT1819CS8 Datasheet - Page 11
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LT1819CS8
Manufacturer Part Number
LT1819CS8
Description
IC OPAMP 9MA 400MHZ DUAL 8-SOIC
Manufacturer
Linear Technology
Datasheet
1.LT1819CS8PBF.pdf
(18 pages)
Specifications of LT1819CS8
Amplifier Type
Voltage Feedback
Number Of Circuits
2
Slew Rate
2500 V/µs
Gain Bandwidth Product
400MHz
Current - Input Bias
2µA
Voltage - Input Offset
200µV
Current - Supply
9mA
Current - Output / Channel
70mA
Voltage - Supply, Single/dual (±)
2.5 V ~ 12.6 V, ±1.25 V ~ 6.3 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Output Type
-
-3db Bandwidth
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LT1819CS8
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Company:
Part Number:
LT1819CS8#PBF
Manufacturer:
LT
Quantity:
401
Part Number:
LT1819CS8#PBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Part Number:
LT1819CS8#TRPBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
APPLICATIONS INFORMATION
Slew Rate
The slew rate of the LT1818/LT1819 is proportional to the
differential input voltage. Highest slew rates are therefore
seen in the lowest gain confi gurations. For example, a 6V
output step with a gain of 10 has a 0.6V input step, whereas
at unity gain there is a 6V input step. The LT1818/LT1819
is tested for slew rate at a gain of –1. Lower slew rates
occur in higher gain confi gurations, whereas the highest
slew rate (2500V/μs) occurs in a noninverting unity-gain
confi guration.
Power Dissipation
The LT1818/LT1819 combine high speed and large output
drive in small packages. It is possible to exceed the maxi-
mum junction temperature specifi cation (150°C) under
certain conditions. Maximum junction temperature (T
is calculated from the ambient temperature (T
dissipation per amplifi er (P
(n) as follows:
Power dissipation is composed of two parts. The fi rst is
due to the quiescent supply current and the second is
due to on-chip dissipation caused by the load current.
The worst-case load-induced power occurs when the
output voltage is at 1/2 of either supply voltage (or the
maximum swing if less than 1/2 the supply voltage).
Therefore P
T
P
P
J
DMAX
DMAX
= T
A
= (V
= (V
+ (n • P
DMAX
+
+
– V
– V
is:
–
D
–
) • (I
) • (I
• θ
JA
SMAX
SMAX
)
D
) + (V
) + (V
) and number of amplifi ers
+
+
/2)2/R
– V
OMAX
L
or
) • (V
A
OMAX
), power
/R
L
J
)
)
Example: LT1819IS8 at 85°C, V
Circuit Operation
The LT1818/LT1819 circuit topology is a true voltage
feedback amplifi er that has the slewing behavior of a cur-
rent feedback amplifi er. The operation of the circuit can
be understood by referring to the Simplifi ed Schematic.
Complementary NPN and PNP emitter followers buffer
the inputs and drive an internal resistor. The input voltage
appears across the resistor, generating a current that is
mirrored into the high impedance node.
Complementary followers form an output stage that buf-
fer the gain node from the load. The input resistor, input
stage transconductance and the capacitor on the high
impedance node determine the bandwidth. The slew rate
is determined by the current available to charge the gain
node capacitance. This current is the differential input
voltage divided by R1, so the slew rate is proportional to
the input step. Highest slew rates are therefore seen in
the lowest gain confi gurations.
P
T
JMAX
DMAX
= 85°C + (2 • 202.5mW) • (150°C/W) = 146°C
= (10V) • (14mA) + (2.5V)2/100Ω = 202.5mW
LT1818/LT1819
S
= ±5V, R
L
= 100Ω
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