MCP6275T-E/SN Microchip Technology, MCP6275T-E/SN Datasheet - Page 15

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MCP6275T-E/SN

Manufacturer Part Number
MCP6275T-E/SN
Description
IC OPAMP 2.0V DUAL W/CS 8SOIC
Manufacturer
Microchip Technology
Datasheet

Specifications of MCP6275T-E/SN

Amplifier Type
General Purpose
Number Of Circuits
2
Output Type
Rail-to-Rail
Slew Rate
0.9 V/µs
Gain Bandwidth Product
2MHz
Current - Input Bias
1pA
Voltage - Input Offset
3000µV
Current - Supply
170µA
Current - Output / Channel
25mA
Voltage - Supply, Single/dual (±)
2 V ~ 6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
-3db Bandwidth
-

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Part Number:
MCP6275T-E/SN
Manufacturer:
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Quantity:
12 000
4.6
An unused op amp in a quad package (MCP6274)
should be configured as shown in
circuits prevent the output from toggling and causing
crosstalk. In Circuit A, R
within its output voltage range (V
buffers this voltage, which can be used elsewhere in
the circuit. Circuit B uses the minimum number of
components and operates as a comparator.
FIGURE 4-6:
4.7
With this family of operational amplifiers, the power
supply pin (V
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good, high frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with nearby analog parts.
4.8
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 10
cause 5 pA of current to flow. This is greater than the
MCP6271/1R/2/3/4/5 family’s bias current at 25°C
(1 pA, typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is illustrated in
Figure
© 2008 Microchip Technology Inc.
¼ MCP6274 (A)
V
V
DD
REF
4-7.
R
R
1
2
Unused Amplifiers
Supply Bypass
PCB Surface Leakage
=
V
DD
DD
V
for single supply) should have a local
DD
------------------
R
1
R
+
2
R
Unused Op Amps.
2
1
and R
12
V
REF
Ω. A 5V difference would
OH
2
¼ MCP6274 (B)
, V
produce a voltage
Figure
OL
V
). The op amp
DD
4-6. These
FIGURE 4-7:
for Inverting Gain.
1.
2.
MCP6271/1R/2/3/4/5
For
Amplifiers (convert current to voltage, such as
photo detectors):
a)
b)
Non-inverting Gain and Unity Gain Buffer:
a)
b)
Connect the guard ring to the non-inverting
input pin (V
to the same reference voltage as the op
amp (e.g., V
Connect the inverting pin (V
with a wire that does not touch the PCB
surface.
Connect the non-inverting pin (V
input with a wire that does not touch the
PCB surface.
Connect the guard ring to the inverting input
pin (V
common mode input voltage.
Inverting
IN
–). This biases the guard ring to the
V
IN
IN
Guard Ring
DD
Gain
+). This biases the guard ring
Example Guard Ring Layout
/2 or ground).
and
V
IN
+
Transimpedance
IN
DS21810F-page 15
–) to the input
IN
V
+) to the
SS

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