AD8592ARM-REEL Analog Devices Inc, AD8592ARM-REEL Datasheet - Page 14
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AD8592ARM-REEL
Manufacturer Part Number
AD8592ARM-REEL
Description
IC OPAMP GP R-R CMOS 3MHZ 10MSOP
Manufacturer
Analog Devices Inc
Datasheet
1.AD8592ARMZ-REEL.pdf
(16 pages)
Specifications of AD8592ARM-REEL
Rohs Status
RoHS non-compliant
Amplifier Type
General Purpose
Number Of Circuits
2
Output Type
Rail-to-Rail
Slew Rate
5 V/µs
Gain Bandwidth Product
3MHz
Current - Input Bias
5pA
Voltage - Input Offset
2000µV
Current - Supply
1.25mA
Current - Output / Channel
250mA
Voltage - Supply, Single/dual (±)
2.5 V ~ 6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
10-MSOP, Micro10™, 10-uMAX, 10-uSOP
-3db Bandwidth
-
Other names
AD8592ARM-REEL
AD8592ARM-REELTR
AD8592ARM-REELTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
AD8592ARM-REEL
Manufacturer:
AD
Quantity:
10 301
Company:
Part Number:
AD8592ARM-REEL
Manufacturer:
SIPEX
Quantity:
10 325
Part Number:
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Manufacturer:
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Quantity:
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AD8591/AD8592/AD8594
The U1-A amplifier is configured as a unity-gain buffer driving
a 1 nF capacitor. The input signal is connected to the noninverting
input, and the sample clock controls the shutdown for that
amplifier. When the sample clock is high, the U1-A amplifier is
active and the output follows V
low, U1-A shuts down with the output of the amplifier going to
a high impedance state, holding the voltage on the C1 capacitor.
The U1-B amplifier is used as a unity-gain buffer to prevent
loading on C1. Because of the low input bias current of the U1-B
CMOS input stage and the high impedance state of the U1-A
output in shutdown, there is little voltage droop from C1 during
the hold period. This circuit can be used with sample frequencies as
high as 500 kHz and as low as 1 Hz. By increasing the C1 value,
lower voltage droop is achieved for very low sample rates.
DIRECT ACCESS ARRANGEMENT FOR PCMCIA
MODEMS (TELEPHONE LINE INTERFACE)
Figure 42 illustrates a 5 V transmit/receive telephone line
interface for 600 Ω systems. It allows full duplex transmission
of signals on a transformer-coupled 600 Ω line in a differential
manner. Amplifier A1 provides gain that can be adjusted to
meet the modem output drive requirements. Both A1 and A2
are configured to apply the largest possible signal on a single
supply to the transformer. Because of the high output current
drive and low dropout voltages of the AD8594, the largest signal
available on a single 5 V supply is approximately 4.5 V p-p into
a 600 Ω transmission system. Amplifier A3 is configured as a
difference amplifier for two reasons. It prevents the transmit
signal from interfering with the receive signal, and it extracts
the receive signal from the transmission line for amplification
by A4. The gain of A4 can be adjusted in the same manner as
the gain of A1 to meet the input signal requirements of the
modem. Standard resistor values permit the use of single
inline package (SIP) format resistor arrays. Couple this with
the 16-lead TSSOP or SOIC footprint of the AD8594, and this
circuit offers a compact, cost-effective solution.
TO TELEPHONE
Figure 42. Single-Supply Direct Access Arrangement for PCMCIA Modems
600Ω
Z
A1, A2 = 1/4 AD8594
A3, A4 = 1/4 AD8594
O
LINE
MIDCOM
671-8005
1:1
T1
6.2V
6.2V
10kΩ
R11
10kΩ
10kΩ
360Ω
R9
R12
R3
12
11
10kΩ
10kΩ
A3
10kΩ
R10
9
R5
R6
Tx GAIN
ADJUST
P1
10
1
2kΩ
7
IN
. When the sample clock goes
9
A1
A2
10kΩ
9
R13
9.09kΩ
R2
6
5
2
3
14.3kΩ
14
15
R14
A4
10kΩ
9
R1
Rx GAIN
ADJUST
2kΩ
16
0.1µF
P2
C1
10µF
0.1µF
C2
SHUTDOWN
+5V
RECEIVE
TRANSMIT
R7
10kΩ
R8
10kΩ
RxA
TxA
Rev. B | Page 14 of 16
SINGLE-SUPPLY DIFFERENTIAL LINE DRIVER
Figure 43 shows a single-supply differential line driver circuit
that can drive a 600 Ω load with less than 0.7% distortion from
20 Hz to 15 kHz with an input signal of 4 V p-p and a single 5 V
supply. The design uses an AD8594 to mimic the performance
of a fully balanced transformer-based solution. However, this
design occupies much less board space, while maintaining low
distortion, and can operate down to dc. Like the transformer-based
design, either output can be shorted to ground for unbalanced
line driver applications without changing the circuit gain of 1.
V
SET: R7, R10, R11 = R2
SET: R6, R12, R13 = R3
R8 and R9 set up the common-mode output voltage equal to
half of the supply voltage. C1 is used to couple the input signal
and can be omitted if the dc voltage of the input is equal to half
of the supply voltage.
The circuit can also be configured to provide additional gain, if
desired. The gain of the circuit is
where:
V
R2 = R7 = R10 = R11
R3 = R6 = R12 = R1
A1, A2 = 1/2 AD8592
GAIN = R3
IN
OUT
22µF
C1
= V
R2
A
V
Figure 43. Low Noise, Single-Supply Differential Line Driver
O1
=
2
3
V
− V
V
OUT
A1
+5V
IN
10
O2
4
10kΩ
10kΩ
10kΩ
R1
=
R10
1
R2
R
R
3
2
R7
10kΩ
R11
10kΩ
2
3
8
7
9
A2
A2
10kΩ
R3
10kΩ
10
R12
4
+5V
10kΩ
R13
1
9
A1
100kΩ
8
7
10kΩ
R6
R9
+5V
R14
50Ω
50Ω
R8
100kΩ
R5
1µF
C2
47µF
47µF
C3
C4
600Ω
R
L
V
V
O1
O2
(7)