MCP6241-E/SN Microchip Technology, MCP6241-E/SN Datasheet - Page 13

• Manufacturer Part Number: MCP6241-E/SN
• Description: IC OPAMP SNGL 1.8V 550KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of MCP6241-E/SN

• Slew Rate: 0.3 V/µs
• Amplifier Type: General Purpose
• Number Of Circuits: 1
• Output Type: Rail-to-Rail
• Gain Bandwidth Product: 550kHz
• Current - Input Bias: 1pA
• Voltage - Input Offset: 5000µV
• Current - Supply: 50µA
• Current - Output / Channel: 23mA
• Voltage - Supply, Single/dual (±): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Op Amp Type: General Purpose
• No. Of Amplifiers: 1
• Bandwidth: 650kHz
• Supply Voltage Range: 1.8V To 5.5V
• Amplifier Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C
• Number Of Channels: 1
• Voltage Gain Db: 110 dB
• Common Mode Rejection Ratio (min): 60 dB
• Input Offset Voltage: 5 mV
• Operating Supply Voltage: 3 V, 5 V
• Supply Current: 0.07 mA
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Details

4.6
In applications where low input bias current is critical,
PCB (printed circuit board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 10
cause 5 pA of current to flow, which is greater than the
MCP6241/1R/1U/2/4 family’s bias current at 25°C
(1 pA, typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure
FIGURE 4-7:
for Inverting Gain.
1.
2.
© 2008 Microchip Technology Inc.
Non-inverting Gain and Unity-Gain Buffer:
a.
b.
Inverting Gain and Transimpedance Amplifiers
(convert current to voltage, such as photo
detectors):
a.
b.
4-7.
PCB Surface Leakage
Connect the non-inverting pin (V
input with a wire that does not touch the
PCB surface.
Connect the guard ring to the inverting input
pin (V
common mode input voltage.
Connect the guard ring to the non-inverting
input pin (V
to the same reference voltage as the op
amp (e.g., V
Connect the inverting pin (V
with a wire that does not touch the PCB
surface.
IN
–). This biases the guard ring to the
V
IN
IN
Guard Ring
DD
+). This biases the guard ring
Example Guard Ring Layout
-
/2 or ground).
12
Ω. A 5V difference would
V
IN
+
IN
–) to the input
IN
V
SS
+) to the
4.7
4.7.1
To minimize the effect of offset voltage in an amplifier
circuit, the impedances at the inverting and non-
inverting inputs need to be matched. This is done by
choosing the circuit resistor values so that the total
resistance at each input is the same.
a summing amplifier circuit.
FIGURE 4-8:
To match the inputs, set all voltage sources to ground
and calculate the total resistance at the input nodes. In
this summing amplifier circuit, the resistance at the
inverting input is calculated by setting V
V
parallel. The total resistance at the inverting input is:
At the non-inverting input, V
source. When V
in parallel. The total resistance at the non-inverting
input is:
To minimize offset voltage and increase circuit
accuracy, the resistor values need to meet the
condition:
OUT
Where:
Where:
MCP6241/1R/1U/2/4
V
V
to ground. In this case, R
R
R
IN2
IN1
VIN –
VIN +
Application Circuits
R
R
X
Y
MATCHING THE IMPEDANCE AT
THE INPUTS
V
= total resistance at the inverting input
R
= total resistance at the inverting
DD
VIN
R
R
R
DD
VIN +
input
G1
G2
–
is set to ground, both R
R
R
Z
=
VIN +
=
Summing Amplifier Circuit.
-------------------------------------------- -
⎛
⎝
---------
R
------------------------ -
⎛
⎝
1
----- -
R
G1
1
MCP6241
=
–
+
X
+
+
1
R
R
VIN
---------
R
DD
----- -
R
F
1
1
1
G1
G2
Y
⎞
⎠
–
, R
is the only voltage
+
+
DS21882D-page 13
R
----- -
R
Figure 4-8
G2
1
Z
F
⎞
⎠
and R
IN1
X
V
and R
, V
OUT
F
IN2
shows
are in
Y
and
are