AD712AQ Analog Devices Inc, AD712AQ Datasheet - Page 13

• Manufacturer Part Number: AD712AQ
• Description: IC OPAMP BIFET DUAL PREC 8CDIP
• Manufacturer: Analog Devices Inc

Specifications of AD712AQ

• Slew Rate: 20 V/µs
• Rohs Status: RoHS non-compliant
• Amplifier Type: J-FET
• Number Of Circuits: 2
• -3db Bandwidth: 4MHz
• Current - Input Bias: 25pA
• Voltage - Input Offset: 300µV
• Current - Supply: 5mA
• Current - Output / Channel: 25mA
• Voltage - Supply, Single/dual (±): 9 V ~ 36 V, ±4.5 V ~ 20 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 8-CDIP (0.300", 7.62mm)
• Op Amp Type: Precision
• No. Of Amplifiers: 2
• Bandwidth: 4MHz
• Supply Voltage Range: ± 4.5V To ± 18V
• Amplifier Case Style: DIP
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Common Mode Rejection Ratio: 88
• Current, Input Bias: 25 pA
• Current, Input Offset: 10 pA
• Current, Offset, Input: 10 pA (Typ.)
• Current, Output: ±25 mA
• Current, Supply: 5 mA (Typ.)
• Harmonic Distortion: 0.0003 %
• Impedance, Thermal: 22 °C/W
• Number Of Amplifiers: Dual
• Package Type: CDIP-8
• Resistance, Input: 3×10^12 Ohms
• Temperature, Operating, Maximum: 85 °C
• Temperature, Operating, Minimum: -40 °C
• Temperature, Operating, Range: -40 to +85 °C
• Voltage, Input: ±20 V (Differential), -11.5 to +14.5 V (Common-Mode)
• Voltage, Noise: 45 nV/sqrt Hz
• Voltage, Offset: 0.3 mV
• Voltage, Offset, Input: 0.3 mV (Typ.)
• Voltage, Output, High: +13.9 V
• Voltage, Output, Low: -13.3 V
• Voltage, Supply: ±15 V
• Output Type: -
• Gain Bandwidth Product: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The photos of Figure 35 and Figure 36 show the dynamic
response of the AD712 in the settling test circuit of Figure 37.
100
0%
90
10
Figure 35. Settling Characteristics 0 V to +10 V Step
Upper Trace: Output of AD712 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)
5V
5mV
(OR EQUIVALENT
FLAT TOP PULSE
GENERATION)
DYNAMICS
DATA
5109
V
IN
10kΩ
4.99kΩ
500ns
0.1µF
–
+
AD712
200Ω
–15V
1/2
10kΩ
+15V
5 TO 18pF
Figure 37. Settling Time Test Circuit
4.99kΩ
0.1µF
HP2835
5kΩ
Rev. H | Page 13 of 20
1.1kΩ
0.47µF
10pF
–15V +15V
+
–
V
OUT
1/2
The input of the settling time fixture is driven by a flat top pulse
generator. The error signal output from the false summing node
of A1 is clamped, amplified by A2, and then clamped again. The
error signal is thus clamped twice: once to prevent overloading
Amplifier A2 and then a second time to avoid overloading the
oscilloscope preamp. The Tektronix oscilloscope preamp type
7A26 was carefully chosen because it does not overload with
these input levels. Amplifier A2 needs to be a very high speed
FET-input op amp; it provides a gain of 10, amplifying the error
signal output of A1.
0.2 TO 0.6pF
10kΩ
0.47µF
5pF
100
0%
90
10
Figure 36. Settling Characteristics 0 V to −10 V Step
Upper Trace: Output of AD712 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)
205Ω
5V
5mV
V
ERROR ×
HP2835
5
TEKTRONIX 7A26
OSCILLOSCOPE
PREAMP
INPUT SECTION
1MΩ
20pF
500ns
AD712