AD8039ARZ Analog Devices Inc, AD8039ARZ Datasheet - Page 5

• Manufacturer Part Number: AD8039ARZ
• Description: IC OPAMP VF DUAL LP LN 8SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD8039ARZ

• Slew Rate: 425 V/µs
• Amplifier Type: Voltage Feedback
• Number Of Circuits: 2
• -3db Bandwidth: 350MHz
• Current - Input Bias: 400pA
• Voltage - Input Offset: 500µV
• Current - Supply: 1mA
• Voltage - Supply, Single/dual (±): 3 V ~ 12 V, ±1.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Op Amp Type: Low Power
• No. Of Amplifiers: 2
• Bandwidth: 350MHz
• Supply Voltage Range: 3V To 12V
• Amplifier Case Style: SOIC
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• Current - Output / Channel: -
• Gain Bandwidth Product: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8038/AD8039
package is limited by the associated rise in junction temperature
(T
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8038/AD8039.
Exceeding a junction temperature of 175°C for an extended
time can result in changes in the silicon devices, potentially
causing failure.
The still-air thermal properties of the package and PCB (θ
ambient temperature (T
package (P
The junction temperature can be calculated as
The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent power
is the voltage between the supply pins (V
quiescent current (I
midsupply, then the total drive power is V
is dissipated in the package and some in the load (V
The difference between the total drive power and the load
power is the drive power dissipated in the package.
J
) on the die. The plastic encapsulating the die locally reaches
T
P
P
D
D
J
= T
= quiescent power + (total drive power − load power)
= [V
D
A
) determine the junction temperature of the die.
S
+ (P
× I
S
D
] + [(V
× θ
S
). Assuming the load (R
JA
)
A
S
/2) × (V
), and total power dissipated in the
OUT
/R
L
)] − [V
D
S
) is the sum of the
/2 × I
S
) multiplied by the
L
) is referenced to
OUT
OUT
Rating
12.6 V
See Figure 5
±V
±4 V
−65°C to +125°C
−40°C to +85°C
300°C
, some of which
2
/R
S
OUT
L
]
× I
JA
OUT
),
Rev. G | Page 5 of 16
).
RMS output voltages should be considered. If R
V
V
worst case, when V
In single-supply operation with R
is V
Airflow increases heat dissipation, effectively reducing θ
addition, more metal directly in contact with the package leads
from metal traces, throughholes, ground, and power planes reduce
the θ
the input leads of high speed op amps as discussed in the
Layout, Grounding, and Bypassing Considerations section.
Figure 5 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC
(125°C/W), 5-lead SC70 (210°C/W), and 8-lead SOT-23
(160°C/W) packages on a JEDEC standard 4-layer board.
θ
OUTPUT SHORT CIRCUIT
Shorting the output to ground or drawing excessive current
from the AD8038/AD8039 will likely cause a catastrophic failure.
ESD CAUTION
Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
JA
S−
S
× I
, as in single-supply operation, then the total drive power is
values are approximations.
OUT
JA
P
OUT
. Care must be taken to minimize parasitic capacitances at
D
2.0
1.0
1.5
0.5
= V
= (V
0
–55
. If the rms signal levels are indeterminate, consider the
S
S
/2.
× I
–25
S
) + (V
SOT-23-8
SC70-5
SOIC-8
OUT
AMBIENT TEMPERATURE (°C)
= V
S
/4)
5
S
2
/R
/4 for R
L
35
L
referenced to V
L
to midsupply
AD8038/AD8039
65
95
L
is referenced to
S−
, worst case
125
JA
. In