LT1168CS8#PBF Linear Technology, LT1168CS8#PBF Datasheet - Page 8

• Manufacturer Part Number: LT1168CS8#PBF
• Description: IC AMP INSTR PREC PROG 8-SOIC
• Manufacturer: Linear Technology
• Type: Instrumentation Ampr

Specifications of LT1168CS8#PBF

• Amplifier Type: Instrumentation
• Number Of Circuits: 1
• Slew Rate: 0.5 V/µs
• Gain Bandwidth Product: 400kHz
• Current - Input Bias: 80pA
• Voltage - Input Offset: 20µV
• Current - Supply: 350µA
• Current - Output / Channel: 32mA
• Voltage - Supply, Single/dual (±): 4.6 V ~ 36 V, ±2.3 V ~ 18 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Number Of Channels: 1
• Number Of Elements: 1
• Power Supply Requirement: Dual
• Common Mode Rejection Ratio: 85dB
• Input Resistance: 1250000@±15VMohm
• Input Offset Voltage: 0.06@±15VmV
• Input Bias Current: 0.0005@±15VnA
• Single Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (typ): 15V
• Power Supply Rejection Ratio: 100dB
• Rail/rail I/o Type: No
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): ±2.3V
• Dual Supply Voltage (max): ±18V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Compliant

LT1168
TYPICAL PERFOR A CE CHARACTERISTICS
8
10
10
34
32
30
28
26
24
22
20
18
16
20
18
16
14
12
10
5
0
5
0
8
6
4
2
0
T
V
R
C
Rising Edge Settling Time
(0.10%)
10
A
0
S
L
L
Change in Input Bias Current for
V
Settling Time (0.1%)
vs Load Capacitance
V
V
T
R
t = 0
= 25°C
= ±15V
= 2k
= 15pF
CM
A
S
CM
INCM
V
T
R
STEP SIZE = 10V
G = 1, RISING EDGE
G = 100, FALLING EDGE
G = 100,
RISING EDGE
= 25°C
CHANGE IN INPUT BIAS CURRENT (pA)
A
= ±15V
S
L
4
= ±10V
= 25°C
= ± 15V
= 1k
= 20V
= 5TΩ
8
LOAD CAPACITANCE (pF)
30
12
5µs/DIV
16
100
G = 1, FALLING EDGE
20
302 N8 (2 LOTS)
313 SO-8 (2 LOTS)
615 TOTAL PARTS
G = 10,
FALLING EDGE
G = 10,
RISING EDGE
24
R
INCM
300
W
28
= 700GΩ
1168 G25
32
1168 G22
1168 G19
U
1000
34
0.10
0.05
0
0.05
0.10
–100
–200
–300
–400
–500
500
400
300
200
100
–10
0
–75 –50 –25
– 2
– 4
– 6
– 8
10
8
6
4
2
0
Input Bias and Offset Current
vs Temperature
V
V
36
34
32
30
28
26
24
22
20
18
8 10 12 14 16 18 20 22 24 26 28 30 32
Settling Time vs Step Size
S
CM
V
G = 1
T
C
R
= ±15V
10
S
A
L
L
Settling Time (0.01%)
vs Load Capacitance
= 0V
= 25°C
= 30pF
= ±15
= 1k
V
T
R
STEP SIZE = 10V
G = 100,
FALLING EDGE
G = 1, RISING EDGE
G = 10, FALLING EDGE
G = 10, RISING EDGE
S
A
L
= ± 15V
= 25°C
= 1k
SETTLING TIME (µs)
TEMPERATURE
30
LOAD CAPACITANCE (pF)
0
TO 0.1%
TO 0.1%
25
100
50
0V
0V
TO 0.01%
TO 0.01%
75
G = 100,
RISING EDGE
I
I
OS
B
300
G = 1,
FALLING
EDGE
100 125
V
V
1168 G23
OUT
OUT
1168 G20
1168 G26
1000
–10
–10
– 5
– 5
0
0
Falling Edge Settling Time
(0.10%)
T
V
R
C
1000
A
S
L
L
100
t = 0
= 25°C
= ±15V
= 2k
= 15pF
10
35
30
25
20
15
10
1
5
0
1
Settling Time vs Gain
1
Undistorted Output Swing
vs Frequency
V
T
∆V
A
S
G = 10, 100, 1000
G = 1
= 25°C
OUT
= ± 15V
= 10V TO 0.01%
5µs/DIV
10
10
FREQUENCY (kHz)
GAIN
100
100
V
T
1168 G24
A
S
= 25°C
= ±15V
1168 G21
0.10
0.05
0
0.05
0.10
1168 G27
1168fa
1000
1000