LTC6404CUD-1#PBF Linear Technology, LTC6404CUD-1#PBF Datasheet - Page 21

• Manufacturer Part Number: LTC6404CUD-1#PBF
• Description: IC AMP/DRIVER DIFF 16-QFN
• Manufacturer: Linear Technology
• Type: ADC Driverr

Specifications of LTC6404CUD-1#PBF

• Applications: Data Acquisition
• Mounting Type: Surface Mount
• Package / Case: 16-WQFN Exposed Pad
• Current - Supply: 27.8mA
• Operating Temperature: 0°C ~ 70°C
• Output Type: Differential, Rail-to-Rail
• Number Of Circuits: 1
• Current - Output / Channel: 85mA
• Amplifier Type: Differential
• Voltage - Supply, Single/dual (±): 2.7 V ~ 5.5 V, ±1.35 V ~ 2.75 V
• -3db Bandwidth: 600MHz
• Slew Rate: 450 V/µs
• Gain Bandwidth Product: 500MHz
• Current - Input Bias: 23µA
• Voltage - Input Offset: 500µV
• No. Of Amplifiers: 1
• Input Offset Voltage: 2mV
• Gain Db Max: 1dB
• Bandwidth: 500MHz
• Supply Voltage Range: 2.7V To 5.25V
• Supply Current: 27.8mA
• Amplifier Case Style: QFN
• Rohs Compliant: Yes
• Number Of Channels: 1
• Number Of Elements: 1
• Power Supply Requirement: Single
• Common Mode Rejection Ratio: 60dB
• Voltage Gain Db: 90dB
• Unity Gain Bandwidth Product (typ): 500MHz
• Input Resistance: 1MOhm
• Single Supply Voltage (typ): 3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Power Supply Rejection Ratio: 60dB
• Rail/rail I/o Type: Rail to Rail Output
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: QFN EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
V
V
mon mode voltage):
and V
voltages:
When the feedback ratios mismatch (Δβ), common mode
to differential conversion occurs.
Setting the differential input to zero (V
gree of common mode to differential conversion is given
by the equation:
In general, the degree of feedback pair mismatch is a
source of common mode to differential conversion of both
signals and noise. Using 1% resistors or better will mitigate
most problems, and will provide about 34dB worst-case of
common mode rejection. Using 0.1% resistors will provide
about 54dB of common mode rejection. A low impedance
ground plane should be used as a reference for both the
input signal source, and the V
V
quality 0.1μF ceramic capacitor to this ground plane, will
further prevent common mode signals from being con-
verted to differential.
There may be concern on how feedback ratio mismatch
affects distortion. Distortion caused by feedback ratio mis-
match using 1% resistors or better is negligible. However,
in single supply level shifting applications where there is
a voltage difference between the input common mode
voltage and the output common mode voltage, resistor
mismatch can make the apparent voltage offset of the
amplifi er appear higher than specifi ed.
The apparent input referred offset induced by feedback
ratio mismatch is derived from the following equation:
INCM
INP
OCM
V
V
V
V
, and V
INDIFF
OSDIFF(APPARENT)
INCM
OUTDIFF
to this ground or bypassing the V
INDIFF
is defi ned as the average of the two input voltages
=
= V
INM
2
1
≈
=
is defi ned as the difference of the input
•
INP
(
(also called the source-referred input com-
V
(
V
OUT
V
INCM
INP
– V
+
INM
+
–
–
≈ (V
V
V
V
INM
OUT
OCM
ICM
)
–
)
– V
•
OCM
β
Δ
OCM
AVG
β
⏐
pin. A direct short of
) • Δβ
V
INDIFF
I
N N DIFF
OCM
= 0), the de-
= 0
with a high
Using the LTC6404-1 in a single supply application on a
single 5V supply with 1% resistors, and the input common
mode grounded, with the V
the worst-case DC offset can induce 25mV of apparent
offset voltage. With 0.1% resistors, the worst case appar-
ent offset reduces to 2.5mV.
Input Impedance and Loading Effects
The input impedance looking into the V
of Figure 1 depends on whether the sources V
V
(V
is simply:
For single ended inputs, because of the signal imbalance
at the input, the input impedance increases over the bal-
anced differential case. The input impedance looking into
either input is:
Input signal sources with non-zero output impedances can
also cause feedback imbalance between the pair of feedback
networks. For the best performance, it is recommended
that the source’s output impedance be compensated for.
If input impedance matching is required by the source,
R1 should be chosen (see Figure 4):
Figure 4. Optimal Compensation for Signal Source Impedance
INM
INP
R
R
R
INP
INP
1
R1 CHOSEN SO THAT R1 || R
R2 CHOSEN TO BALANCE R1 || R
= –V
are fully differential. For balanced input sources
=
V
S
= R
R
=
R
INM
INM
R
INM
INM
INM
R
–
), the input impedance seen at either input
•
S
R
R
= R
=
S
S
R2 = R
⎛
⎜
⎝
R1
I
1
– •
S
2
1
|| R1
INM
⎛
⎝ ⎜
R
R
= R
S
INM
OCM
R
I
S
I
R
+
R
R
F
pin biased at mid-supply,
R
I
I
F
⎞
⎠ ⎟
⎞
⎟
⎠
–
+
LTC6404
INP
R
R
F
F
+
–
or V
6404 F04
INM
INP
21
input
and
6404f