LT1801CS8#PBF Linear Technology, LT1801CS8#PBF Datasheet - Page 14

• Manufacturer Part Number: LT1801CS8#PBF
• Description: IC PREC OPAMP R-R DUAL LP 8-SOIC
• Manufacturer: Linear Technology
• Type: General Purpose Amplifierr

Specifications of LT1801CS8#PBF

• Amplifier Type: General Purpose
• Number Of Circuits: 2
• Output Type: Rail-to-Rail
• Slew Rate: 20 V/µs
• Gain Bandwidth Product: 70MHz
• Current - Input Bias: 400nA
• Voltage - Input Offset: 700µV
• Current - Supply: 1.8mA
• Current - Output / Channel: 50mA
• Voltage - Supply, Single/dual (±): 2.3 V ~ 12.6 V, ±1.15 V ~ 6.3 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Rail/rail I/o Type: Rail to Rail Input/Output
• Number Of Elements: 2
• Unity Gain Bandwidth Product: 80MHz
• Common Mode Rejection Ratio: 85dB
• Input Offset Voltage: 3mV
• Input Bias Current: 1.5uA
• Single Supply Voltage (typ): 3/5/9/12V
• Dual Supply Voltage (typ): ±3/±5V
• Voltage Gain In Db: 98.59dB
• Power Supply Rejection Ratio: 78dB
• Power Supply Requirement: Single/Dual
• Shut Down Feature: No
• Single Supply Voltage (min): 2.3V
• Single Supply Voltage (max): 12.6V
• Dual Supply Voltage (min): ±1.15V
• Dual Supply Voltage (max): ±6.3V
• Technology: BiCOM
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Compliant

APPLICATIONS INFORMATION
LT1801/LT1802
Circuit Description
The LT1801/LT1802 have an input and output signal range
that covers from the negative power supply to the positive
power supply. Figure 1 depicts a simplifi ed schematic of the
amplifi er. The input stage is comprised of two differential
amplifi ers, a PNP stage Q1/Q2 and an NPN stage Q3/Q4
that are active over the different ranges of common mode
input voltage. The PNP differential pair is active between
the negative supply to approximately 1.2V below the posi-
tive supply. As the input voltage moves closer toward the
positive supply, the transistor Q5 will steer the tail current I
to the current mirror Q6/Q7, activating the NPN differential
pair and the PNP pair becomes inactive for the rest of the
input common mode range up to the positive supply. Also
at the input stage, devices Q17 to Q19 act to cancel the bias
current of the PNP input pair. When Q1-Q2 are active, the
current in Q16 is controlled to be the same as the current
in Q1-Q2, thus the base current of Q16 is nominally equal
to the base current of the input devices. The base current
of Q16 is then mirrored by devices Q17-Q19 to cancel the
base current of the input devices Q1-Q2.
14
V
V
+
–
Q16
+
I
2
+IN
–IN
Q17
Q18
ESDD1
ESDD4
V
V
+
–
V
V
–
+
ESDD2
ESDD3
Figure 1. LT1801/LT1802 Simplifi ed Schematic Diagram
D6
D5
D8
D7
Q19
Q4
Q7
D1
D2
Q3
1
Q5
Q6
A pair of complementary common emitter stages Q14/Q15
that enable the output to swing from rail to rail constructs
the output stage. The capacitors C2 and C3 form the
local feedback loops that lower the output impedance at
high frequency. These devices are fabricated on Linear
Technology’s proprietary high speed complementary
bipolar process.
Power Dissipation
The LT1801 amplifi er is offered in a small package, SO-8,
which has a thermal resistance of 190°C/W, θ
a need to ensure that the die’s junction temperature should
not exceed 150°C. Junction temperature T
from the ambient temperature T
and thermal resistance θ
The power dissipation in the IC is the function of the sup-
ply voltage, output voltage and the load resistance. For a
given supply voltage, the worst-case power dissipation
P
DMAX
V
BIAS
T
J
Q1
+
= T
D3
D4
Q2
occurs at the maximum supply current and the
A
I
1
+ (P
Q10
D
• θ
Q11
JA
)
Q9
R3
R1
Q12
JA
Q8
R4
R2
:
C
C
+
A
V
OUTPUT BIAS
, power dissipation P
Q13
–
R5
BUFFER
I
3
AND
C2
C1
J
18012 F01
JA
is calculated
. So there is
Q15
Q14
OUT
18012fc
D