MCP6L4T-E/ST Microchip Technology, MCP6L4T-E/ST Datasheet - Page 11

• Manufacturer Part Number: MCP6L4T-E/ST
• Description: IC OPAMP 2.8MHZ 2.7V 14-TSSOP
• Manufacturer: Microchip Technology

Specifications of MCP6L4T-E/ST

• Slew Rate: 2.3 V/µs
• Amplifier Type: General Purpose
• Number Of Circuits: 4
• Output Type: Rail-to-Rail
• Gain Bandwidth Product: 2.8MHz
• Current - Input Bias: 1pA
• Voltage - Input Offset: 1000µV
• Current - Supply: 200µA
• Current - Output / Channel: 20mA
• Voltage - Supply, Single/dual (±): 2.7 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Op Amp Type: General Purpose
• No. Of Amplifiers: 4
• Bandwidth: 2.8MHz
• Supply Voltage Range: 2.7V To 6V
• Amplifier Case Style: TSSOP
• No. Of Pins: 14
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: MCP6L4T-E/STTR

4.0
The MCP6L1/1R/2/4 family of op amps is manufac-
tured using Microchip’s state of the art CMOS process.
They are unity-gain stable and suitable for a wide range
of general purpose applications.
4.1
4.1.1
The MCP6L1/1R/2/4 op amps are designed to prevent
phase inversion when the input pins exceed the supply
voltages.
ing both supplies without any phase reversal.
4.1.2
In order to prevent damage and/or improper operation
of these amplifiers, the circuit they are in must limit the
currents (and voltages) at the input pins (see
Section 1.1
Figure 4-1
protecting these inputs. The internal ESD diodes
prevent the input pins (V
far below ground, and the resistors R
possible current drawn out of the input pins. Diodes D
and D
going too far above V
V
FIGURE 4-1:
Inputs.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (V
Figure
need to limit the usable voltage range.
© 2009 Microchip Technology Inc.
DD
.
2
2-7. Applications that are high impedance may
V
V
prevent the input pins (V
APPLICATION INFORMATION
Inputs
1
2
R
R
Figure 2-10
1
2
PHASE REVERSAL
INPUT VOLTAGE AND CURRENT
LIMITS
shows the recommended approach to
>
>
R
R
“Absolute
V
V
1
2
SS
SS
D
1
CM
– (minimum expected V
– (minimum expected V
) is below ground (V
DD
shows an input voltage exceed-
Protecting the Analog
D
2
, and dump any currents onto
IN
+ and V
2 mA
2 mA
Maximum
MCP6LX
R
V
IN
IN
3
DD
+ and V
–) from going too
1
and R
Ratings †”).
1
2
)
)
2
IN
SS
limit the
–) from
); see
1
4.1.3
The Common Mode Input Voltage Range (V
includes ground in single-supply systems (V
does not include V
input behaves linearly as long as the Common Mode
Input Voltage (V
ically V
Figure 4-3
same voltage as the inverting input, V
below V
FIGURE 4-2:
Limited V
4.2
The output voltage range of the MCP6L1/1R/2/4 op
amps is V
(maximum) when R
and V
tion.
4.3
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (R
feedback loop’s stability by making the output load
resistive at higher frequencies; the bandwidth will
usually be decreased.
FIGURE 4-3:
stabilizes large capacitive loads.
Bench measurements are helpful in choosing R
Adjust R
Figure
DD
SS
2-14) has reasonable overshoot (e.g., 4%).
R
R
DD
ISO
= 5.0V. Refer to
Rail-to-Rail Output
Capacitive Loads
G
N
– 0.3V to V
OUT
shows a unity gain buffer. Since V
DD
– 1.2V (typically) for correct operation.
NORMAL OPERATION
so that a small signal step response (see
V
1
– 35 mV (minimum) and V
MCP6L1/1R/2/4
Range.
CM
MCP6LX
) is kept within the V
DD
L
R
DD
MCP6LX
= 10 kΩ is connected to V
. This means that the amplifier
F
Unity Gain Buffer has a
Output Resistor, R
ISO
– 1.2V at +25°C).
Figure 2-13
in
Figure
R
C
ISO
L
DS22135A-page 11
4-3) improves the
for more informa-
OUT
V
CMR
2
must be kept
SS
ISO
limits (typ-
OUT
V
+ 35 mV
SS
OUT
), but
is the
CMR
DD
ISO
/2
)
.