SAF-C164CI-8E28M DB Infineon Technologies, SAF-C164CI-8E28M DB Datasheet - Page 71

• Manufacturer Part Number: SAF-C164CI-8E28M DB
• Description: IC MCU 16BIT OTP MQFP-80-1
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C164CI-8E28M DB

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: OTP
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-SQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: SAFC164CI8E28MDBT; SP000057421; SP000106781

Demultiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
Parameter
Data float after RdCS
(no RW-delay)
Address hold after
RdCS, WrCS
Data hold after WrCS
1)
2)
3)
Data Sheet
RW-delay and
Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
t
1)
A
refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
Symbol
t
t
t
t
68
55
57
A
+
CC -6 +
CC 6 +
SR –
t
C
+
t
min.
F
Max. CPU Clock
(80 ns at 25 MHz CPU clock without waitstates)
t
F
t
= 25 MHz
F
67
max.
0 +
–
–
t
F
1 / 2TCL = 1 to 25 MHz
min.
–
-6 +
TCL - 14 +
t
F
Variable CPU Clock
t
F
max.
TCL - 20
+ 2
–
–
t
A
C164CL/SL
V2.0, 2001-05
+
C164CI/SI
t
F
1)
Unit
ns
ns
ns