MC9S08DV48CLF Freescale Semiconductor, MC9S08DV48CLF Datasheet - Page 39
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MC9S08DV48CLF
Manufacturer Part Number
MC9S08DV48CLF
Description
IC MCU 48K FLASH 2K RAM 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DV48CLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DV48CLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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To maintain I/O states for pins that were configured as general-purpose I/O before entering stop2, the user
must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers
before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to
PPDACK, then the pins will switch to their reset states when PPDACK is written.
For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that
interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.
3.6.3
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. Refer to
Mode” and
Freescale Semiconductor
On-Chip Peripheral Modules in Stop Modes
Section 3.6.1, “Stop3 Mode
1
2
3
4
CPU
RAM
Flash
Parallel Port Registers
ACMP
ADC
IIC
MCG
MSCAN
RTC
SCI
SPI
TPM
Voltage Regulator
XOSC
I/O Pins
BDM
LVD/LVW
Requires the asynchronous ADC clock and LVD to be enabled, else in standby.
IRCLKEN and IREFSTEN set in MCGC1, else in standby.
Requires the RTC to be enabled, else in standby.
Requires the LVD or BDC to be enabled.
Peripheral
MC9S08DV60 Series Data Sheet, Rev 3
Table 3-2. Stop Mode Behavior
” for specific information on system behavior in stop modes.
Optionally On
States Held
Standby
Stop2
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
6
7
3
Mode
Optionally On
Optionally On
Optionally On
Optionally On
Optionally On
Optionally On
Optionally On
States Held
Standby
Standby
Standby
Standby
Standby
Standby
Standby
Standby
Standby
Stop3
Off
Chapter 3 Modes of Operation
Section 3.6.2, “Stop2
1
2
3
4
5
39
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