MC9S08DZ60CLC Freescale Semiconductor, MC9S08DZ60CLC Datasheet - Page 231
![IC MCU 60K FLASH 4K RAM 32-LQFP](/photos/12/46/124644/mc9s08dz60clc_sml.jpg)
MC9S08DZ60CLC
Manufacturer Part Number
MC9S08DZ60CLC
Description
IC MCU 60K FLASH 4K RAM 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DZ60CLC
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
DEMO9S08DZ60 - BOARD DEMOEVB9S08DZ60 - BOARD EVAL FOR 9S08DZ60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ60CLC
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC9S08DZ60CLCR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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1
2
12.3.5
This register contains the interrupt enable bits for the interrupt flags described in the CANRFLG register.
Read: Anytime
Write: Anytime when not in initialization mode
Freescale Semiconductor
Redundant Information for the most critical CAN bus status which is “bus-off”. This only occurs if the Tx error counter exceeds
a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state
skips to RxOK too. Refer also to TSTAT[1:0] coding in this register.
To ensure data integrity, do not read the receive buffer registers while the RXF flag is cleared. For MCUs with dual CPUs,
reading the receive buffer registers while the RXF flag is cleared may result in a CPU fault condition.
OVRIF
Field
RXF
1
0
Reset:
2
W
R
MSCAN Receiver Interrupt Enable Register (CANRIER)
Overrun Interrupt Flag — This flag is set when a data overrun condition occurs. If not masked, an error interrupt
is pending while this flag is set.
0
1
Receive Buffer Full Flag — RXF is set by the MSCAN when a new message is shifted in the receiver FIFO. This
flag indicates whether the shifted buffer is loaded with a correctly received message (matching identifier,
matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message
from the RxFG buffer in the receiver FIFO, the RXF flag must be cleared to release the buffer. A set RXF flag
prohibits the shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, a receive interrupt
is pending while this flag is set.
0
1
WUPIE
The CANRIER register is held in the reset state when the initialization mode
is active (INITRQ=1 and INITAK=1). This register is writable when not in
initialization mode (INITRQ=0 and INITAK=0).
The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization
mode.
0
7
No data overrun condition
A data overrun detected
No new message available within the RxFG
The receiver FIFO is not empty. A new message is available in the RxFG
Figure 12-9. MSCAN Receiver Interrupt Enable Register (CANRIER)
Table 12-9. CANRFLG Register Field Descriptions (continued)
CSCIE
6
0
MC9S08DZ60 Series Data Sheet, Rev. 4
RSTATE1
0
5
RSTATE0
NOTE
4
0
Description
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
TSTATE1
0
3
TSTATE0
2
0
OVRIE
0
1
RXFIE
0
0
231
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