MC9S08DN60CLF Freescale Semiconductor, MC9S08DN60CLF Datasheet - Page 215
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MC9S08DN60CLF
Manufacturer Part Number
MC9S08DN60CLF
Description
IC MCU 60K FLASH 2K RAM 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DN60CLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DN60CLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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12.1.1
Features of the SPI module include:
12.1.2
This section includes block diagrams showing SPI system connections, the internal organization of the SPI
module, and the SPI clock dividers that control the master mode bit rate.
12.1.2.1
Figure 12-2
device initiates all SPI data transfers. During a transfer, the master shifts data out (on the MOSI pin) to the
slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively
exchanges the data that was in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock
output from the master and an input to the slave. The slave device must be selected by a low level on the
slave select input (SS pin). In this system, the master device has configured its SS pin as an optional slave
select output.
Freescale Semiconductor
•
•
•
•
•
•
•
Master or slave mode operation
Full-duplex or single-wire bidirectional option
Programmable transmit bit rate
Double-buffered transmit and receive
Serial clock phase and polarity options
Slave select output
Selectable MSB-first or LSB-first shifting
7
6
Features
Block Diagrams
shows the SPI modules of two MCUs connected in a master-slave arrangement. The master
SPI System Block Diagram
5
GENERATOR
SPI SHIFTER
MASTER
CLOCK
4
3
2
1
0
Figure 12-2. SPI System Connections
MC9S08DN60 Series Data Sheet, Rev 3
MOSI
MISO
SPSCK
SS
SPSCK
MOSI
MISO
SS
Chapter 12 Serial Peripheral Interface (S08SPIV3)
7
SLAVE
6
5
SPI SHIFTER
4
3
2
1
0
215
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