R5F21217JFP#U0 Renesas Electronics America, R5F21217JFP#U0 Datasheet - Page 362
R5F21217JFP#U0
Manufacturer Part Number
R5F21217JFP#U0
Description
IC R8C/20 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/21r
Datasheet
1.R5F21216JFP.pdf
(503 pages)
Specifications of R5F21217JFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21217JFP#U0R5F21217JFP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R5F21217JFP#U0R5F21217JFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
135
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R8C/20 Group, R8C/21 Group
Rev.2.00 Aug 27, 2008
REJ09B0250-0200
16.3.8
16.3.8.1
16.3.8.2
Set the IICSEL bit in the PMR register to 1 (select I
The following actions must be performed to use the I
Either of the following actions must be performed to use the I
•
•
(a) Use the MOV instruction to set bits MST and TRS.
(b) When arbitration is lost, confirm the contents of bits MST and TRS. If the contents are other than the
(a) In master receive mode while the RDRF bit in the ICSR register is set to 1, read the ICDRR register
(b) In master receive mode, set the RCVD bit in the ICCR1 register to 1 (disables the next receive
Transfer rate
Set the transfer rate by 1/1.8 or faster than the fastest rate of the other masters. For example, if the fastest
transfer rate of the other masters is set to 400 kbps, the I
223 kbps (= 400/1.18) or more.
Bits MST and TRS in the ICCR1 register setting
Notes on I
MST bit set to 0 and the TRS bit set to 0 (slave receive mode), set the MST bit to 0 and the TRS bit to 0
again.
before the rising edge of the 8th clock.
operation) to perform 1-byte communications.
Master Receive Mode
Multimaster Operation
Page 344 of 458
2
C Bus Interface
2
C bus interface function) to use I
2
C bus interface in multimaster operation.
2
2
C-bus transfer rate in this MCU should be set to
C bus interface in master receive mode.
16. Clock Synchronous Serial Interface
2
C bus interface.
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