MCL908QY2DWE Freescale Semiconductor, MCL908QY2DWE Datasheet - Page 130

• Manufacturer Part Number: MCL908QY2DWE
• Description: IC MCU 8BIT 1.5K FLASH 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCL908QY2DWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 2MHz
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

Timer Interface Module (TIM)
14.9.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers does the following:
CHxF — Channel x Flag Bit
CHxIE — Channel x Interrupt Enable Bit
MSxB — Mode Select Bit B
130
•
•
•
•
•
•
•
•
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM counter registers matches the value in the TIM channel x registers.
Clear CHxF by reading the TIM channel x status and control register with CHxF set and then writing a
0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing
a 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing
of CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE
bit.
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM
channel 0 status and control register.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
Flags input captures and output compares
Enables input capture and output compare interrupts
Selects input capture, output compare, or PWM operation
Selects high, low, or toggling output on output compare
Selects rising edge, falling edge, or any edge as the active input capture trigger
Selects output toggling on TIM overflow
Selects 0% and 100% PWM duty cycle
Selects buffered or unbuffered output compare/PWM operation
Address: $0025
Address: $0028
Reset:
Reset:
Read:
Read:
Write:
Write:
CH0F
CH1F
Bit 7
Bit 7
0
0
0
0
Figure 14-7. TIM Channel Status and Control
TSC0
TSC1
= Unimplemented
MC68HLC908QY/QT Family Data Sheet, Rev. 3
CH0IE
CH1IE
6
0
6
0
Registers (TSC0:TSC1)
MS0B
5
0
5
0
0
MS0A
MS1A
4
0
4
0
ELS0B
ELS1B
3
0
3
0
ELS0A
ELS1A
2
0
2
0
TOV0
TOV1
1
0
1
0
Freescale Semiconductor
CH0MAX
CH1MAX
Bit 0
Bit 0
0
0