MC9S12XD256VAG Freescale Semiconductor, MC9S12XD256VAG Datasheet - Page 967

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MC9S12XD256VAG

Manufacturer Part Number
MC9S12XD256VAG
Description
IC MCU 256K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XD256VAG

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
14K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
Part Number:
MC9S12XD256VAG
Manufacturer:
FREESCAL
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MC9S12XD256VAG
Manufacturer:
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Quantity:
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A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by
4 consecutive samples of an active level directly or indirectly.
The filters are continuously clocked by the bus clock in run and wait mode. In stop mode, the clock
is generated by an RC-oscillator in the port integration module. To maximize current saving the
RC oscillator runs only if the following condition is true on any pin individually:
Sample count <= 4 and interrupt enabled (PIE = 1) and interrupt flag not set (PIF = 0).
23.0.9
All peripheral ports T, S, M, P, H, J, AD0, and AD1 start up as general purpose inputs after reset.
Depending on the external mode pin condition, the external bus interface related ports A, B, C, D,
E, and K start up as general purpose inputs on reset or are configured for their alternate functions.
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
Expanded Bus Pin Functions
Figure 23-77. Interrupt Glitch Filter on Port P, H, and J (PPS = 0)
Uncertain
1. These values include the spread of the oscillator frequency over
Ignored
Pulse
Valid
temperature, voltage and process.
Table 23-69. Pulse Detection Criteria
t
pign
Figure 23-78. Pulse Illustration
3 < t
t
pval
t
t
pulse
pulse
STOP
pulse
< 4
3
4
uncertain
t
pulse
Bus clocks
Bus clocks
Bus clocks
Unit
Mode
t
pign
t
t
pulse
pulse
< t
STOP
pulse
t
t
pign
1
pval
< t
pval

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