MC9S08RE16FDER Freescale Semiconductor, MC9S08RE16FDER Datasheet
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MC9S08RE16FDER
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MC9S08RE16FDER Summary of contents
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MC9S08RC8/16/32/60 MC9S08RD8/16/32/60 MC9S08RE8/16/32/60 MC9S08RG32/60 Data Sheet HCS08 Microcontrollers MC9S08RG60/D Rev. 1.11 06/2005 freescale.com ...
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MC9S08RG60 Data Sheet Covers: MC9S08RC8/16/32/60 MC9S08RD8/16/32/60 MC9S08RE8/16/32/60 MC9S08RG32/60 MC9S08RG60/D Rev. 1.11 06/2005 ...
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... Date 1.11 06/2005 ® This product contains SuperFlash Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2005. All rights reserved. Description of Changes Added 48 QFN package and official mechanical drawings; suppled TBD values for IRO V ...
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... Chapter 12 Serial Communications Interface (S08SCIV1).................... 147 Chapter 13 Serial Peripheral Interface (S08SPIV3) ............................... 163 Chapter 14 Analog Comparator (S08ACMPV1) ..................................... 179 Chapter 15 Development Support .......................................................... 183 Appendix A Electrical Characteristics..................................................... 205 Appendix B Ordering Information and Mechanical Drawings............... 219 Freescale Semiconductor MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 List of Chapters 5 ...
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... Stop2 Mode ....................................................................................................................31 3.6.3 Stop3 Mode ....................................................................................................................32 3.6.4 Active BDM Enabled in Stop Mode ...............................................................................33 3.6.5 LVD Reset Enabled ........................................................................................................33 3.6.6 On-Chip Peripheral Modules in Stop Mode ...................................................................33 Freescale Semiconductor Contents Title Chapter 1 Introduction Chapter 2 Pins and Connections Chapter 3 Modes of Operation MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Page ...
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... Low-Voltage Detect (LVD) System ................................................................................................62 5.6.1 Power-On Reset Operation .............................................................................................63 5.6.2 LVD Reset Operation .....................................................................................................63 5.6.3 LVD Interrupt and Safe State Operation ........................................................................63 5.6.4 Low-Voltage Warning (LVW) ........................................................................................63 5.7 Real-Time Interrupt (RTI) ...............................................................................................................64 8 Title Chapter 4 Memory Chapter 5 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Page Freescale Semiconductor ...
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... Stack Pointer (SP) ...........................................................................................................89 7.2.4 Program Counter (PC) ....................................................................................................89 7.2.5 Condition Code Register (CCR) .....................................................................................89 7.3 Addressing Modes ...........................................................................................................................90 7.3.1 Inherent Addressing Mode (INH) ..................................................................................91 7.3.2 Relative Addressing Mode (REL) ..................................................................................91 7.3.3 Immediate Addressing Mode (IMM) .............................................................................91 Freescale Semiconductor Title Chapter 6 Parallel Input/Output Chapter 7 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Page 9 ...
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... Carrier Generator Data Registers (CMTCGH1, CMTCGL1, CMTCGH2, and CMTCGL2) ..............................................................................................................118 8.6.2 CMT Output Control Register (CMTOC) ....................................................................120 8.6.3 CMT Modulator Status and Control Register (CMTMSC) ..........................................121 8.6.4 CMT Modulator Data Registers (CMTCMD1, CMTCMD2, CMTCMD3, and CMTCMD4) .............................................................................................................122 10 Title Chapter 8 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Page Freescale Semiconductor ...
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... Timer Counter Registers (TPM1CNTH:TPM1CNTL) ................................................140 10.7.3 Timer Counter Modulo Registers (TPM1MODH:TPM1MODL) ................................141 10.7.4 Timer Channel n Status and Control Register (TPM1CnSC) .......................................142 10.7.5 Timer Channel Value Registers (TPM1CnVH:TPM1CnVL) .......................................143 Freescale Semiconductor Title Chapter 9 Keyboard Interrupt (S08KBIV1) Chapter 10 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Page ...
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... Functional Description ..................................................................................................................167 13.3.1 SPI Clock Formats ........................................................................................................168 13.3.2 SPI Pin Controls ...........................................................................................................170 13.3.2.1 SPSCK1 — SPI Serial Clock ........................................................................170 13.3.2.2 MOSI1 — Master Data Out, Slave Data In ..................................................170 12 Title Chapter 11 Chapter 12 Chapter 13 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Page Freescale Semiconductor ...
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... BDC Registers and Control Bits ...................................................................................196 15.4.1.1 BDC Status and Control Register (BDCSCR) ..............................................197 15.4.1.2 BDC Breakpoint Match Register (BDCBKPT) ............................................198 15.4.2 System Background Debug Force Reset Register (SBDFR) ........................................198 Freescale Semiconductor Title Chapter 14 Chapter 15 Development Support MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 ...
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... A.9.1 Control Timing ...............................................................................................................212 A.9.2 Timer/PWM (TPM) Module Timing .............................................................................213 A.9.3 SPI Timing ......................................................................................................................214 A.10 FLASH Specifications ...................................................................................................................218 Ordering Information and Mechanical Drawings B.1 Ordering Information ....................................................................................................................219 B.2 Mechanical Drawings ....................................................................................................................220 14 Title Appendix A Electrical Characteristics Appendix B MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Page Freescale Semiconductor ...
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... Full-duplex or single-wire bidirectional option • Programmable transmit bit rate • Double-buffered transmit and receive • Serial clock phase and polarity options • Slave select output • Selectable MSB-first or LSB-first shifting Freescale Semiconductor option MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Table 1-1 for the 15 ...
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... During output mode, pullups are disengaged. FLASH RAM 32K/60K 2K/2K 8/16K/32K/60K 1K/1K/2K/2K 8/16K/32K/60K 1K/1K/2K/2K MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Development Support chapter) (1) ACMP SCI SPI Yes Yes Yes Yes Yes No No Yes No Freescale Semiconductor ...
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... Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and rising edge is selected (KBEDGn = 1). Figure 1-1. MC9S08RC/RD/RE/RG Block Diagram Table 1-2 lists the functional versions of the on-chip modules. Freescale Semiconductor INTERNAL BUS DEBUG MODULE (DBG) 8-BIT KEYBOARD ...
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... RTI oscillator as its clock source. 18 Table 1-2. Block Versions Module SYSTEM TPM RTICLKS CONTROL LOGIC RTI ÷ BUSCLK 2 BDC MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Version SPI SCI CMT RAM FLASH ACMP FLASH has frequency requirements for program and erase operation. See Appendix A. Freescale Semiconductor ...
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... This section describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. 2.2 Device Pin Assignment PTB0/TxD1 1 PTB1/RxD1 PTB2 PTB3 PTB4 IRO PTB5 PTB6 PTB7/TPM1CH1 11 Figure 2-1. MC9S08RC/RD/RE/RG in 44-Pin LQFP Package Freescale Semiconductor MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 PTA0/KBI1P0 33 PTD6/TPM1CH0 32 PTD5/ACMP1+ 31 PTD4/ACMP1– 30 EXTAL ...
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... Figure 2-3. MC9S08RC/RD/RE/RG in 28-Pin SOIC Package and 28-Pin PDIP Package PTB2 IRO MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 24 PTD6/TPM1CH0 23 PTD5/ACMP1+ 22 PTD4/ACMP1– 21 EXTAL XTAL 20 19 PTD2/IRQ PTD1/RESET 18 PTD0/BKGD/MS 17 PTA4/KBI1P4 28 PTA3/KBI1P3 27 PTA2/KBI1P2 26 PTA1/KBI1P1 25 PTA0/KBI1P0 24 PTD6/TPM1CH0 23 EXTAL 22 XTAL 21 PTD1/RESET 20 PTD0/BKGD/MS 19 PTC7/SS1 18 PTC6/SPSCK1 17 PTC5/MISO1 16 PTC4/MOSI1 15 Freescale Semiconductor ...
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... NC 12 Figure 2-4. MC9S08RC/RD/RE/RG in 48-Pin QFN Package 2.3 Recommended System Connections Figure 2-5 shows pin connections that are common to almost all MC9S08RC/RD/RE/RG application systems. A more detailed discussion of system connections follows. Freescale Semiconductor MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Pins and Connections PTA0/KBI1P0 34 ...
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... PORT B PTB4 PTB5 I/O AND PTB6 PTB7/TPM1CH1 PERIPHERAL INTERFACE TO PTC0/KBI2P0 PTC1/KBI2P1 APPLICATION PTC2/KBI2P2 SYSTEM PTC3/KBI2P3 PORT C PTC4/MOSI1 PTC5/MISO1 PTC6/SPSCK1 PTC7/SS1 PTD0/BKGD/MS PTD1/RESET PTD2/IRQ PTD3 PORT D PTD4/ACMP1– PTD5/ACMP1+ PTD6/TPM1CH0 IRO PTE0 PTE1 PTE2 PTE3 PORT E PTE4 PTE5 PTE6 PTE7 Freescale Semiconductor ...
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... Never connect any significant capacitance to the reset pin because that would interfere with the circuit and sequence that detects the source of reset external capacitance prevents the reset pin from rising to a valid logic 1 before the reset sample point, all resets will appear to be external resets. Freescale Semiconductor should be a low-inductance resistor such as a carbon F ...
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... Input/Output." For information about how and when on-chip peripheral systems use these pins, refer to the appropriate chapter from Table 24 Carrier Modulator Timer (CMT) Module Chapter NOTE 2-1. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 for a Table 2-2.) Immediately after reset, Chapter 6, “Parallel Freescale Semiconductor ...
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... Signal Properties Summary Table 2-2 summarizes I/O pin characteristics. These characteristics are determined by the way the common pin interfaces are hardwired to internal circuits. Freescale Semiconductor Table 2-1. Pin Sharing References Reference Chapter 9, “Keyboard Interrupt (S08KBIV1)” Chapter 10, “Timer/PWM Module (S08TPMV1)” ...
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... Available only in 32-, 44-, and 48-pin packagess SWC SWC SWC SWC SWC SWC SWC SWC SWC (4) SWC Output-only when configured as PTD0 pin. Pullup enabled. (3) SWC Output-only when configured as PTD1 pin. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 (3) Comments . PTA0 should not Freescale Semiconductor ...
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... When configured for the IRQ function, this pin will have a pullup device enabled when the IRQ is set for falling edge detection and a pulldown device enabled when the IRQ is set for rising edge detection. Freescale Semiconductor Table 2-2. Signal Properties (continued) ...
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... Pins and Connections 28 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
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... When the BKGD/MS pin is low at the rising edge of reset • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed • When encountering a BDC breakpoint • When encountering a DBG breakpoint Freescale Semiconductor MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 29 ...
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... The active background mode is used to program a bootloader or user application program into the FLASH program memory before the MCU is operated in run mode for the first time. When the MC9S08RC/RD/RE/RG is shipped from the Freescale Semiconductor factory, the FLASH program memory is usually erased so there is no program that could be executed in run mode until the FLASH memory is initially programmed ...
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... When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned off, except for the RAM. The voltage regulator low-power standby state the ACMP. Upon entry Freescale Semiconductor Table 3-1. Stop Mode Behavior RAM ...
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... When RTIS2:RTIS1:RTIS0 = 0:0:0, the real-time interrupt function and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in that case the real-time interrupt cannot wake the MCU from stop. 32 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
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... When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks are kept alive to the background debug logic, clocks to the peripheral systems are halted to reduce power consumption. Freescale Semiconductor Development Support chapter of this data sheet. If ENBDM is set when ...
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... If the MCU is configured to go into stop2 or stop1 mode, the CMT module will be reset upon wakeup from stop and must be reinitialized. Voltage Regulator — The voltage regulator enters a low-power standby state when the MCU enters any of the stop modes unless the LVD reset function is enabled or BDM is enabled. 34 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. Freescale Semiconductor ...
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... Direct-page registers ($0000 through $0045 for 32K and 60K parts, and $0000 through $003F for 16K and 8K parts) • High-page registers ($1800 through $182B) • Nonvolatile registers ($FFB0 through $FFBF) Freescale Semiconductor MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 35 ...
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... RAM 1024 BYTES $043F $043F $0440 $0440 UNIMPLEMENTED 5056 BYTES $17FF $17FF $1800 $1800 HIGH PAGE REGISTERS $182B $182B $182C $182C UNIMPLEMENTED 51156 BYTES $BFFF $C000 $DFFF $E000 FLASH 8192 BYTES $FFFF $FFFF MC9S08RC/RD/RE8 Chapter 5, “Resets, Freescale Semiconductor ...
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... The analog comparator (ACMP) module is not included on the MC9S08RD devices. This vector location is unused for those devices. 3. The SCI module is not included on the MC9S08RC devices. This vector location is unused for those devices. Freescale Semiconductor Figure 4-2. Reset and Interrupt Vectors Vector ...
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... Shaded cells with dashes indicate unused or reserved bit locations that could read 0s. 38 can use the more efficient direct addressing mode, which requires 4-3, the whole address in column one is shown in bold. In MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Table 4 summary of all Table Freescale Semiconductor 4-1, ...
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... SL7 $0024 CMTOC IROL $0025 CMTMSC EOCF $0026 CMTCMD1 MB15 $0027 CMTCMD2 MB7 $0028 CMTCMD3 SB15 $0029 CMTCMD4 SB7 Freescale Semiconductor Table 4-1. Direct-Page Register Summary PTAD6 PTAD5 PTAD4 PTAPE6 PTAPE5 PTAPE4 — — — PTADD6 PTADD5 PTADD4 PTBD6 PTBD5 PTBD4 ...
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... LVD BKGDPE — — — — — — ID11 ID10 ID9 ID3 ID2 ID1 0 RTIS2 RTIS1 Freescale Semiconductor Bit 0 — — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — — LSBFE SPC0 SPR0 0 — Bit 0 Bit 0 0 BDFR RSTPE — ...
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... Address Register Name Bit 7 $FFB0– NVBACKKEY $FFB7 $FFB8– Reserved — $FFBC — $FFBD NVPROT FPOPEN $FFBE Reserved — $FFBF NVOPT KEYEN Freescale Semiconductor LVDACK LVDIE SAFE LVWACK 0 0 — — — — — — ...
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... FLASH erase and programming operations, in-application programming is also possible through other software-controlled communication paths. For a more detailed discussion of in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I, Freescale Semiconductor document order number HCS08RMv1/D. 42 ;point one past RAM ...
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... Parameter Byte program Byte program (burst) Page erase Mass erase 1. Excluding start/end overhead Freescale Semiconductor (FCDIV)”). This register can be written only ) is used by the command processor to time FCLK = 1/f FCLK FCLK Table 4-4. Program and Erase Times ...
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... The command sequence must be completed by clearing FCBEF to launch the command. burst programming. The FCDIV register must be initialized before using any FLASH commands. This must be done only once following a reset. 44 NOTE Figure 4 flowchart for executing all of the commands except for MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
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... A5 through A0. A new row begins when addresses A5 through A0 are all zero. The first byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst Freescale Semiconductor START 0 ...
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... WRITE COMMAND TO FCMD WRITE 1 TO FCBEF TO LAUNCH COMMAND (2) AND CLEAR FCBEF YES FPVIO OR FACCERR ? NO YES NEW BURST COMMAND ? NO 0 FCCF ? 1 DONE MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 (1) Required only once after reset. (2) Wait at least four cycles before checking FCBEF or FCCF. ERROR EXIT Freescale Semiconductor ...
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... One use for block protection is to block protect an area of FLASH memory for a bootloader program. This bootloader program then can be used to erase the rest of the FLASH memory and reprogram it. Because the bootloader is protected, it remains intact even if MCU power is lost during an erase and reprogram operation. Freescale Semiconductor MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Section 4.6.4, “FLASH Protection Memory ...
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... Writing 1 to KEYACC in the FCNFG register. This makes the FLASH module interpret writes to the backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to be compared against the key rather than as the first step in a FLASH program or erase command. 48 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
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... Bit 7 of this register is a read-only status flag. Bits 6 through 0 may be read at any time but can be written only one time. Before any erase or programming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory system within acceptable limits. Freescale Semiconductor MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Memory ...
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... MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. DIV2 DIV1 Program/Erase Timing Pulse (5 µs Min, 6.7 µs Max) 5 µs 5 µs 5 µs 5 µs 5 µs 6.7 µs Freescale Semiconductor 0 DIV0 0 Eqn. 4-1 Eqn. 4-2 ...
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... Secure SEC01:SEC00 changes to 1:0 after successful backdoor key entry or a successful blank check of FLASH. 4.6.3 FLASH Configuration Register (FCNFG) Bits 7 through 5 may be read or written at any time. Bits 4 through 0 always read 0 and cannot be written. Freescale Semiconductor Figure 4-6. FLASH Options Register (FOPT) Table 4-7 ...
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... FLASH locations at the high address end of the FLASH (see locations cannot be erased or programmed KEYACC 0 0 Table 4-8. FCNFG Field Descriptions Description Section 4. FPS2 FPS1 FPS0 (1) (1) (1) Table 4-9. FPROT Field Descriptions Description Table 4-10 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. “Security." and Table 4-11). Protected FLASH Freescale Semiconductor ...
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... No redirection if FPOPEN = 0, or FNORED = 1. 2. Reset vector is not redirected. 3. Use for 60K version only. When protecting all of 32K version memory, use FPOPEN = 0. Freescale Semiconductor Protected Block Size 512 bytes 1 Kbytes 2 Kbytes 4 Kbytes 8 Kbytes 16 Kbytes ...
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... After a blank check command is completed and FCCF = 1, FBLANK = 1 indicates the FLASH array is completely erased (all $FF FPVIOL FACCERR 0 0 Figure 4-9. FLASH Status Register (FSTAT) Table 4-12. FSTAT Field Descriptions Description MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. FBLANK Section 4.4.5, “Access Errors." FACCERR Freescale Semiconductor ...
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... Mass erase (all FLASH) All other command codes are illegal and generate an access error not necessary to perform a blank check command after a mass erase operation. Only blank check is required as part of the security unlocking mechanism. Freescale Semiconductor Execution,” for a detailed discussion of FLASH 5 4 ...
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... Memory 56 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
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... The I bit in the condition code register (CCR) is set to block maskable interrupts until the user program has a chance to initialize the stack pointer (SP) and system control settings forced to $00FF at reset. Freescale Semiconductor MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Table ...
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... CPU status so processing resumes where it was before the interrupt. Other than the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events such 58 Section 5.8.4, “System Options Register MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 (SOPT),” for Freescale Semiconductor ...
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... SP points at the next available location on the stack, which is the address that is one less than the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred. Freescale Semiconductor NOTE MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Resets, Interrupts, and System Confi ...
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... CONDITION CODE REGISTER ACCUMULATOR * INDEX REGISTER (LOW BYTE X) PROGRAM COUNTER HIGH PROGRAM COUNTER LOW TOWARD HIGHER ADDRESSES * High byte (H) of index register is not automatically stacked. Figure 5-1. Interrupt Stack Frame MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 SP AFTER INTERRUPT STACKING SP BEFORE THE INTERRUPT Freescale Semiconductor ...
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... CCR the CPU will finish the current instruction; stack the PCL, PCH and CCR CPU registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. Freescale Semiconductor MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Resets, Interrupts, and System Configuration ...
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... SCI error FE FEIE PF PFIE TOIE TPM overflow CH1IE TPM channel 1 CH0IE TPM channel 0 IRQIE IRQ pin LVDIE Low-voltage detect — Software interrupt COPE Watchdog timer LVD LVDRE Low-voltage detect RSTPE External pin — Illegal opcode — Illegal address Freescale Semiconductor SPI ...
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... LVWF bit in the system power management status and control 2 (SPMSC2) LVW register must be checked before initiating any FLASH program or erase operation. Freescale Semiconductor level. Both the POR bit and the LVD bit in SRS are set LVD drops below V and the LVD circuit is confi ...
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... These bits are used to configure the IRQ function, report status, and acknowledge IRQ events. 64 Memory chapter of this data sheet for the absolute address MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 (SRTISC),” for detailed Freescale Semiconductor ...
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... BDFR in the SBDFR register, none of the status bits in SRS will be set. Writing any value to this register address clears the COP watchdog timer without affecting the contents of this register. The reset state of these bits depends on what caused the MCU to reset. Freescale Semiconductor 5 4 ...
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... Reset not caused by LVD trip or POR 1 Reset caused by LVD trip or POR COP ILOP ILAD Writing any value to SRS address clears COP watchdog timer (2) (2) (2) Figure 5-3. System Reset Status (SRS) Table 5-3. SRS Field Descriptions Description MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. (1) 0 LVD Freescale Semiconductor ...
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... BDFR is writable only through serial background debug commands, not from user programs. Field 0 Background Debug Force Reset — A serial background command such as WRITE_BYTE may be used to BDFR allow an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. Freescale Semiconductor Table 5-4 ...
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... PTD1, which is an output only general purpose I/O. This pin always defaults to RESET function after any reset. 0 RESET pin disabled. 1 RESET pin enabled STOPE 0 1 Table 5-5. SOPT Field Descriptions Description 18 cycles of BUSCLK). 20 cycles of BUSCLK). MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. BKGDPE Freescale Semiconductor 0 RSTPE 1 ...
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... Figure 5-7. System Device Identification Register — Low (SDIDL) Field 7:0 Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The ID[7:0] MC9S08RC/RD/RE/RG32/60 is hard coded to the value $004 and the MC9S08RC/RD/RE8/16 is hard coded to the value $003. Freescale Semiconductor 5 4 REV1 REV0 ID11 (1) ...
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... Characteristics,” for the tolerance on these values. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. RTIS2 RTIS1 5-9. External Clock Source Period = t ext Disable periodic wakeup timer t x 256 ext t x 1024 2048 4096 8192 ext t x 16384 ext t x 32768 ex Table A-9 Freescale Semiconductor 0 RTIS0 0 (2) for details. ...
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... Low-Voltage Detect Reset Enable — This bit enables the LVD reset function. This bit can be written only once LVDRE after a reset and additional writes have no meaning or effect set following a POR and is unaffected by any other resets, including an LVD reset. 0 LVDF does not generate hardware resets. 1 Force an MCU reset when LVDF = 1. Freescale Semiconductor 5 4 LVDIE SAFE LVDRE ...
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... Stop1, full power down, mode enabled if PDC set. 1 Stop2, partial power down, mode enabled if PDC set PPDF 0 0 transitions below the trip point or after reset and V Supply Table 5-11. SPMSC2 Field Descriptions Description MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. PDC PPDACK already below V Supply Freescale Semiconductor 0 PPDC 0 . LVW ...
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... Eight port B pins shared with SCI and TPMCH1 • Eight port C pins shared with KBI2 and SPI • Seven port D pins shared with TPMCH0, ACMP, IRQ, RESET, and BKGD/MS • Eight port E pins Freescale Semiconductor NOTE MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Chapter 2, “Pins and 73 ...
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... PTB7 as a timer pin. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Chapter 2, “Pins and Bit 0 PTA3/ PTA2/ PTA1/ PTA0/ KBI1P3 KBI1P2 KBI1P1 KBI1P0 Controls,” for more Keyboard Interrupt Bit 0 PTB1/ PTB0/ PTB3 PTB2 RxD1 TxD1 Controls,” for more chapter for more information Freescale Semiconductor ...
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... BKGD/MS pin becomes the background communications input/output pin. PTD0 can be configured general-purpose output pin through software control. Refer to Chapter 5, “Resets, Interrupts, and System information about using this pin. The PTD1/RESET pin is configured for the RESET function during reset and following reset. Freescale Semiconductor PTC6/ ...
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... This ensures that the pin will not be driven with an old data value that happened the port data register. 76 Input/Output,” PTE6 PTE5 PTE4 Figure 6-5. Port E Pin Names Section 6.4, “Parallel I/O MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 for more information about using PTD6 Bit 0 PTE3 PTE2 PTE1 PTE0 Controls,” for more Freescale Semiconductor ...
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... I/O registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. Freescale Semiconductor NOTE MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Parallel Input/Output ...
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... PTAD5 PTAD4 PTAD3 0 0 Figure 6-6. Port A Data Register (PTAD) Table 6-1. PTAD Field Descriptions Description 5 4 PTAPE5 PTAPE4 PTAPE3 0 0 Table 6-2. PTAPE Field Descriptions Description MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. PTAD2 PTAD1 PTAPE2 PTAPE1 Freescale Semiconductor 0 PTAD0 0 0 PTAPE0 0 ...
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... Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is driven out the corresponding MCU pin. Reset forces PTBD to all 0s, but these 0s are not driven out on the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. Freescale Semiconductor 5 4 PTADD5 ...
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... Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn PTBPE5 PTBPE4 PTBPE3 0 0 Table 6-5. PTBPE Field Descriptions Description 5 4 PTBDD5 PTBDD4 PTBDD3 0 0 Table 6-6. PTBDD Field Descriptions Description MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. PTBPE2 PTBPE1 PTBDD2 PTBDD1 Freescale Semiconductor 0 PTBPE0 0 0 PTBDD0 0 ...
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... Pullup Enable for Port C Bits — For port C pins that are inputs, these read/write control bits determine whether PTCPE[7:0] internal pullup devices are enabled. For port C pins that are configured as outputs, these bits are ignored and the internal pullup devices are disabled. 0 Internal pullup device disabled. 1 Internal pullup device enabled. Freescale Semiconductor 5 4 PTCD5 PTCD4 PTCD3 ...
Page 82
... PTCDD5 PTCDD4 PTCDD3 0 0 Table 6-9. PTCDD Field Descriptions Description 5 4 PTDD5 PTDD4 PTDD3 0 0 Figure 6-15. Port D Data Register (PTDD) Table 6-10. PTDD Field Descriptions Description MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. PTCDD2 PTCDD1 PTDD2 PTDD1 Freescale Semiconductor 0 PTCDD0 0 0 PTDD0 0 ...
Page 83
... Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for PTDDD[6:0] PTDD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn. Freescale Semiconductor 5 4 PTDPE5 PTDPE4 ...
Page 84
... PTED5 PTED4 PTED3 0 0 Figure 6-18. Port E Data Register (PTED) Table 6-13. PTED Field Descriptions Description 5 4 PTEPE5 PTEPE4 PTEPE3 0 0 Table 6-14. PTED Field Descriptions Description MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. PTED2 PTED1 PTEPE2 PTEPE1 Freescale Semiconductor 0 PTED0 0 0 PTEPE0 0 ...
Page 85
... Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for PTEDD[7:0] PTED reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn. Freescale Semiconductor 5 4 PTEDD5 PTEDD4 ...
Page 86
... Parallel Input/Output 86 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
Page 87
... This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several instructions and enhanced addressing modes were added to improve C compiler effi ...
Page 88
... For compatibility with the earlier M68HC05 Family forced to 0x00 during reset. Reset has no effect on the contents ACCUMULATOR A 16-BIT INDEX REGISTER H:X INDEX REGISTER (LOW STACK POINTER PROGRAM COUNTER CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
Page 89
... For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1/D. CONDITION CODE REGISTER Freescale Semiconductor Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2 ...
Page 90
... Instructions such as BRCLR, BRSET, CBEQ, and DBNZ use one addressing mode to specify the location 90 Table 7-1. CCR Register Field Descriptions Description MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
Page 91
... Indexed Addressing Mode Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and two that use the stack pointer as the base reference. Freescale Semiconductor Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2) MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 ...
Page 92
... The CPU performs a few special operations that are similar to instructions but do not have opcodes like other CPU instructions. In addition, a few instructions such as STOP and WAIT directly affect other MCU circuitry. This section provides additional information about these operations. 92 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
Page 93
... The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the global I bit in the CCR and it is associated with an instruction opcode within the program not asynchronous to program execution. Freescale Semiconductor Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2) Resets, Interrupts, and System Configuration MC9S08RC/RD/RE/RG Data Sheet, Rev ...
Page 94
... Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user program. 94 chapter for more details. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
Page 95
... Two’s complement overflow indicator, bit Half carry, bit Interrupt mask, bit Negative indicator, bit Zero indicator, bit Carry/borrow, bit 0 (carry out of bit 7) CCR activity notation – = Bit not affected Freescale Semiconductor Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2) MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Table 7-2. 95 ...
Page 96
... The assembler will calculate the 8-bit signed offset and include it in the object code for this instruction. Address modes INH = Inherent (no operands) IMM = 8-bit or 16-bit immediate DIR = 8-bit direct EXT = 16-bit extended 96 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
Page 97
... ASRA ASRX Arithmetic Shift Right ASR oprx8,X ASR ,X ASR oprx8,SP BCC rel Branch if Carry Bit Clear Freescale Semiconductor Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2) Description A ← (A) + (M) + (C) A ← (A) + (M) SP ← (SP sign extended to a 16-bit value H:X ← (H: sign extended to a 16-bit value A ← ...
Page 98
... REL 2B rr – – – – – – REL 2D rr – – – – – – REL 26 rr – – – – – – REL 2A rr – – – – – – REL 20 rr Freescale Semiconductor ...
Page 99
... COM ,X COM oprx8,SP CPHX opr16a CPHX #opr16i Compare Index Register CPHX opr8a (H:X) with Memory CPHX oprx8,SP Freescale Semiconductor Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2) Description Branch if (Mn Uses 3 Bus Cycles Branch if (Mn ← ← (PC) + 0x0002 push (PCL); SP ← (SP) – 0x0001 push (PCH) ...
Page 100
... DIR BD dd EXT IX2 IX1 – – – IMM A6 ii DIR B6 dd EXT IX2 IX1 SP2 9ED6 ee ff SP1 9EE6 ff 0 – – – IMM 45 jj DIR 55 dd EXT 9EAE IX2 9EBE ee ff IX1 9ECE ff SP1 9EFE ff Freescale Semiconductor ...
Page 101
... Stack Pull H (Index Register PULH High) from Stack Pull X (Index Register PULX Low) from Stack ROL opr8a ROLA ROLX Rotate Left through Carry ROL oprx8,X ROL ,X ROL oprx8,SP Freescale Semiconductor Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2) Description X ← ( ← (M) (M) ...
Page 102
... INH 8E 0 – – – DIR BF dd EXT IX2 IX1 SP2 9EDF ee ff SP1 9EEF ff – – IMM A0 ii DIR B0 dd EXT IX2 IX1 SP2 9ED0 ee ff SP1 9EE0 ff – – 1 – – – INH 83 Freescale Semiconductor ...
Page 103
... Low) to Accumulator TXS Transfer Index Reg Enable Interrupts; Wait WAIT for Interrupt 1 Bus clock frequency is one-half of the CPU clock frequency. Freescale Semiconductor Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2) Description CCR ← (A) X ← (A) A ← (CCR) (M) – 0x00 (A) – 0x00 (X) – ...
Page 104
... IMM 2 DIR 3 EXT 3 IX2 TXA AIX STX STX STX INH 2 IMM 2 DIR 3 EXT 3 IX2 Opcode HCS08 Cycles Hexadecimal SUB Instruction Mnemonic Addressing Mode Number of Bytes 1 IX Freescale Semiconductor SUB SUB 2 IX1 CMP CMP 2 IX1 SBC SBC 2 IX1 CPX CPX 2 IX1 1 IX ...
Page 105
... Indexed, 16-Bit Offset DD DIR to DIR IMD IMM to DIR IX+D IX+ to DIR DIX+ DIR to IX+ Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E) Freescale Semiconductor Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2) Table 7-3. Opcode Map (Sheet Read-Modify-Write Control 9E60 6 NEG 3 SP1 ...
Page 106
... Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2) 106 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
Page 107
... The RESET pin contains integrated pullup device enabled if reset enabled (RSTPE = 1) 5. High current drive 6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and rising edge is selected (KBEDGn = 1). Figure 8-1. MC9S08RC/RD/RE/RG Block Diagram Freescale Semiconductor INTERNAL BUS DEBUG MODULE (DBG) 8-BIT KEYBOARD ...
Page 108
... CMT module. This is so the CMT can be configured as a modulo timer for generating periodic interrupts without causing pin activity. 108 PRIMARY/SECONDARY SELECT CARRIER CARRIER OUT ( MODULATOR GENERATOR CMT REGISTERS AND BUS INTERFACE INTERNAL BUS MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 MODULATOR OUT TRANSMITTER OUTPUT IIREQ Freescale Semiconductor IRO PIN ...
Page 109
... The transmitter output block controls the state of the infrared out pin (IRO). The modulator output is gated on to the IRO pin when the modulator/carrier generator is enabled. A summary of the possible modes is shown in Freescale Semiconductor Carrier Modulator Transmitter (CMT) Block Description Figure 8-2. When operating in time mode, the user independently defines Table 8-1 ...
Page 110
... IRO pin when modulator gate is open. CG Setting the EXSPC bit causes subsequent modulator cycles spaces (modulator out not asserted) for the duration of the modulator period (mark and space times IROL bit controls state of IRO pin. NOTE Figure 8-3. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Comment Freescale Semiconductor ...
Page 111
... In the general case, the carrier generator output frequency is Where: 0 < Highcount < 256 and 0 < Lowcount < 256 Freescale Semiconductor Carrier Modulator Transmitter (CMT) Block Description CMTCGH2 CMTCGH1 =? CLK 8-BIT UP COUNTER CLR ...
Page 112
... FSK protocols that require successive bursts of different frequencies). The MCGEN bit in the CMTMSC register must be set to enable the modulator timer. 112 Highcount Duty Cycle = --------------------------------------------------------------------- Highcount + Lowcount MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Eqn. 8-4 Freescale Semiconductor ...
Page 113
... CMTCMD1:CMTCMD2 and CMTCMD3:CMTCMD4 are the decimal values of the concatenated registers. If the modulator is disabled while the t carrier high time (t into an illegal state and end the curent cycle before the programmed value. Make sure to program t illegal state. Freescale Semiconductor Carrier Modulator Transmitter (CMT) Block Description MODE CLOCK CONTROL LOAD MODULATOR GATE . ...
Page 114
... MARK SPACE Figure 8-5 for an example of the output for both baseband ) is generated with a high count of $01 and CG NOTE Figure 8-5 and Figure 8-6 are for the purpose of MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 MARK Freescale Semiconductor ...
Page 115
... EXSPC Operation in Time Mode To calculate the length of an extended space in time or baseband modes, add the mark and space times and multiply by the number of modulation periods that EXSPC is set. Freescale Semiconductor Carrier Modulator Transmitter (CMT) Block Description = (CMTCMD1:CMTCMD2 + 1) ÷ CMTCMD3:CMTCMD4 ÷ f ...
Page 116
... A polarity bit in the CMTOC register enables the IRO pin to be high true or low true. 116 + ( (number of modulation periods) mark space Figure 8-7. NOTE CLEAR EXSPC Figure 8-7. Extended Space Operation ) + ( space p mark space s mark ) + ( space s mark space p mark MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. +... space +... space s Freescale Semiconductor Eqn. 8-9 Eqn. 8-10 Eqn. 8-11 ...
Page 117
... IRO pin from being asserted while in stop mode. This may require a time-out period from the time that the MCGEN bit is cleared to allow the last modulator cycle to complete. Freescale Semiconductor Carrier Modulator Transmitter (CMT) Block Description MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 ...
Page 118
... The primary carrier high and low time values are unaffected out of reset. These bits must be written to nonzero values before the carrier generator is enabled to avoid spurious results. 118 5 4 PH5 PH4 PH3 u u Table 8-3. CMTCGH1 Field Descriptions Description MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. PH2 PH1 Section 8.5.2.1, Section 8.5.2.3, “FSK Freescale Semiconductor 0 PH0 u ...
Page 119
... Mode"), this register pair and the primary register pair are alternatively selected under control of the modulator. The secondary carrier high and low time values are unaffected out of reset. These bits must be written to nonzero values before the carrier generator is enabled when operating in FSK mode. Freescale Semiconductor Carrier Modulator Transmitter (CMT) Block Description 5 ...
Page 120
... IRO pin disabled 1 IRO pin enabled as output 120 5 4 SL5 SL4 SL3 u u Table 8-6. CMTCGL2 Field Descriptions Description IROPEN 0 0 Table 8-7. CMTOC Field Descriptions Description MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. SL2 SL1 Section 8.5.2.1, Section 8.5.2.3, “FSK Freescale Semiconductor 0 SL0 ...
Page 121
... Mode." This bit is cleared by reset. This bit is not double buffered and should not be written to during a transmission. 0 Baseband mode disabled 1 Baseband mode enabled 2 FSK Mode Select — The FSK bit enables FSK operation. FSK 0 CMT operates in time or baseband mode 1 CMT operates in FSK mode Freescale Semiconductor Carrier Modulator Transmitter (CMT) Block Description 5 4 CMTDIV0 EXSPC BASE 0 0 Table 8-8 ...
Page 122
... Description Table 8-9. Sample Register Summary MB14 MB13 MB12 MB6 MB5 MB4 SB14 SB13 SB12 SB6 SB5 SB4 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. MB11 MB10 MB9 MB3 MB2 MB1 SB11 SB10 SB9 SB3 SB2 SB1 Freescale Semiconductor 0 MB8 MB0 SB8 SB0 ...
Page 123
... The voltage measured on the pulled up PTA0 pin will be less than V internal gates connected to this pin are pulled all the way to V pins with enabled pullup resistors will have an unloaded measurement Freescale Semiconductor NOTE MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 . The DD . All other ...
Page 124
... PTB2 PTB1/RxD1 PTB0/TxD1 PTC7/SS1 PTC6/SPSCK1 PTC5/MISO1 PTC4/MOSI1 PTC3/KBI2P3 PTC2/KBI2P2 PTC1/KBI2P1 PTC0/KBI2P0 PTD6/TPM1CH0 PTD5/ACMP1+ PTD4/ACMP1– PTD3 PTD2/IRQ PTD1/RESET PTD0/BKGD/MS 8 PTE7– PTE0 NOTE 1 IRO NOTE 5 . Also, PTA0 does not pullup to V when internal DD DD Freescale Semiconductor NOTES1, 2 NOTES 1, 5 NOTE 1 NOTES ...
Page 125
... Synchronous logic is used to detect edges. Prior to detecting an edge, enabled keyboard inputs in a KBI module must be at the deasserted logic level. A falling edge is detected when an enabled keyboard input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. Freescale Semiconductor V DD CLR ...
Page 126
... Some MCU systems have more than one KBI, so register names include placeholder characters to identify which KBI is being referenced. For example, KBIxSC refers to the KBIx status and control register and KBI2SC is the status and control register for KBI2. 126 Memory chapter of this data sheet for the absolute address MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
Page 127
... KBI port bits 3 through 0 can detect falling edges-only or falling edges and low levels. KBI port bits 7 through 4 can be configured to detect either: • Rising edges-only or rising edges and high levels (KBEDGn = 1) • Falling edges-only or falling edges and low levels (KBEDGn = 0) 0 Edge-only detection. 1 Edge-and-level detection. Freescale Semiconductor 5 4 KBF KBEDG5 KBEDG4 ...
Page 128
... Bit n of KBI port is a general-purpose I/O pin not associated with the KBI. 1 Bit n of KBI port enabled as a keyboard interrupt input 128 5 4 KBIPE5 KBIPE4 KBIPE3 0 0 Table 9-2. KBIxPE Field Descriptions Description MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. KBIPE2 KBIPE1 Freescale Semiconductor 0 KBIPE0 0 ...
Page 129
... Prescale taps for divide 16, 32, 64, or 128 — External clock input shared with TPM1CH0 timer channel pin • 16-bit modulus register to control counter range • Timer system enable • One interrupt per channel plus terminal count interrupt Freescale Semiconductor MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 129 ...
Page 130
... PTA7/KBI1P7– PTA1/KBI1P1 NOTES1, 2 PTA0/KBI1P0 PTB7/TPM1CH1 PTE6 PTB5 PTB4 NOTES 1, 5 PTB3 PTB2 PTB1/RxD1 PTB0/TxD1 PTC7/SS1 PTC6/SPSCK1 PTC5/MISO1 PTC4/MOSI1 NOTE 1 PTC3/KBI2P3 PTC2/KBI2P2 PTC1/KBI2P1 PTC0/KBI2P0 PTD6/TPM1CH0 PTD5/ACMP1+ PTD4/ACMP1– NOTES PTD3 PTD2/IRQ PTD1/RESET PTD0/BKGD/MS 8 PTE7– PTE0 NOTE 1 IRO NOTE 5 Freescale Semiconductor ...
Page 131
... The central component of the TPM is the 16-bit counter that can operate as a free-running counter, a modulo counter up-/down-counter when the TPM is configured for center-aligned PWM. The TPM counter (when operating in normal up-counting mode) provides the timing reference for the input capture, Freescale Semiconductor Figure 10-2 shows the structure of a TPM. Some MCUs ...
Page 132
... The TPM has center-aligned PWM capabilities controlled by the CPWMS control bit in TPM1SC. When CPWMS is set to 1, timer counter TPM1CNT changes to an up-/down-counter and all channels in the associated TPM act as center-aligned PWM channels. When CPWMS = 0, each channel can 132 Pins and Connections MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 chapter for additional information Freescale Semiconductor ...
Page 133
... This corresponds to the end of a PWM period. (The $0000 count value corresponds to the center of a period.) Freescale Semiconductor Section 10.7.1, “Timer Status and Control Register MC9S08RC/RD/RE/RG Data Sheet, Rev ...
Page 134
... TPM are configured for input capture or output compare functions. The period of this PWM signal is determined by the setting in the modulus register (TPM1MODH:TPM1MODL). The duty cycle is determined by the setting in the timer channel value 134 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
Page 135
... If TPM1CnVH:TPM1CnVL is a positive value (bit 15 clear) and is greater than the (nonzero) modulus setting, the duty cycle will be 100 percent because the duty cycle compare will never occur. This implies the usable range of periods set by the modulus register is $0001 through $7FFE ($7FFF if Freescale Semiconductor OVERFLOW PERIOD ...
Page 136
... Writing to TPM1CnSC cancels any values written to the channel value registers and resets the coherency mechanism for TPM1CnVH:TPM1CnVL. 136 COUNT = 0 OUTPUT OUTPUT COMPARE COMPARE (COUNT UP) (COUNT DOWN) PULSE WIDTH 2 x PERIOD 2 x MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 COUNT = TPM1MODH:TPM Freescale Semiconductor ...
Page 137
... When a channel is configured as an output compare channel, the interrupt flag is set each time the main timer counter matches the 16-bit value in the channel value register. The flag is cleared by the 2-step sequence described in Section 10.6.1, “Clearing Timer Interrupt Freescale Semiconductor chapter for absolute interrupt vector addresses, priority, and local Flags.” MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 ...
Page 138
... TPM registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 138 Section 10.6.1, “Clearing Timer Interrupt Memory chapter of this data sheet for the absolute address MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Flags.” Freescale Semiconductor ...
Page 139
... Prescale Divisor Select — This 3-bit field selects one of eight divisors for the TPM clock input as shown in PS[2:0] Table 10-3. This prescaler is located after any clock source synchronization or clock source selection affects whatever clock source is selected to drive the TPM system. Freescale Semiconductor CPWMS ...
Page 140
... Fixed system clock (XCLK) External source (TPM1 Ext Clk) Table 10-3. Prescale Divisor Selection Any write to TPM1CNTH clears the 16-bit counter Any write to TPM1CNTL clears the 16-bit counter MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. TPM Clock Source Divided- 128 Freescale Semiconductor 0 Bit Bit 0 0 ...
Page 141
... It is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well before a new overflow. An alternative approach is to reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first counter overflow will occur. Freescale Semiconductor 5 4 ...
Page 142
... This is also the setting required for channel 0 when the TPM1CH0 pin is used as an external clock input. 142 MSnB MSnA ELSnB Description Table 10-5 Table 10-5, these bits select the polarity of the input edge that triggers an MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. ELSnA 0 0 Table 10-5. for a summary of channel mode and setup Freescale Semiconductor ...
Page 143
... R Bit Reset 0 0 Figure 10-12. Timer Channel Value Register Low (TPM1CnVL) Freescale Semiconductor Mode Pin not used for TPM channel; use as an external clock for the TPM or 00 revert to general-purpose I/O 01 Capture on rising edge only 10 Input capture Capture on falling edge only ...
Page 144
... When both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching mechanism may be manually reset by writing to the TPM1CnSC register. This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations. 144 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
Page 145
... The SCI module shares pins with PTB0 and PTB1 port pins. When the SCI is enabled, the pins are controlled by the SCI module. Figure 11 device-level block diagram with the SCI highlighted. Freescale Semiconductor MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 145 ...
Page 146
... PTB2 PTB1/RxD1 PTB0/TxD1 PTC7/SS1 PTC6/SPSCK1 PTC5/MISO1 PTC4/MOSI1 PTC3/KBI2P3 PTC2/KBI2P2 PTC1/KBI2P1 PTC0/KBI2P0 PTD6/TPM1CH0 PTD5/ACMP1+ PTD4/ACMP1– PTD3 PTD2/IRQ PTD1/RESET PTD0/BKGD/MS 8 PTE7– PTE0 NOTE 1 IRO NOTE 5 . Also, PTA0 does not pullup to V when internal DD DD Freescale Semiconductor NOTES1, 2 NOTES 1, 5 NOTE 1 NOTES ...
Page 147
... Modes of Operation See Section 12.3, “Functional Description,” for a detailed description of SCI operation in the different modes. • 8- and 9- bit data modes • Stop modes — SCI is halted during all stop modes • Loop modes Freescale Semiconductor MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 147 ...
Page 148
... TDRE TIE TC TCIE Figure 12-1. SCI Transmitter Block Diagram MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 shows the receiver portion of the SCI.) LOOPS RSRC LOOP TO RECEIVE CONTROL DATA IN TO TxD PIN SCI CONTROLS TxD TO TxD PIN LOGIC TxD DIRECTION Tx INTERRUPT REQUEST Freescale Semiconductor ...
Page 149
... SCI. INTERNAL BUS 16 × BAUD RATE CLOCK FROM RxD PIN DATA RECOVERY LOOPS SINGLE-WIRE LOOP CONTROL RSRC FROM TRANSMITTER PE PT Freescale Semiconductor (READ-ONLY) SCID – Rx BUFFER DIVIDE 11-BIT RECEIVE SHIFT REGISTER WAKE WAKEUP LOGIC ILT RDRF ...
Page 150
... When 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in 150 Memory chapter of this data sheet for the absolute address SBR12 SBR11 Description SBR5 SBR4 SBR3 Description MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. SBR10 SBR9 SBR8 Table 12- SBR2 SBR1 SBR0 Table 12-1. Freescale Semiconductor ...
Page 151
... Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total PT number the data character, including the parity bit, is odd. Even parity means the total number the data character, including the parity bit, is even. 0 Even parity. 1 Odd parity. Freescale Semiconductor RSRC M ...
Page 152
... I/O pin. 2 Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin Receiver off. 1 Receiver on. 152 RIE ILIE Description Idle,” for more details. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. RWU SBK Freescale Semiconductor ...
Page 153
... TC is cleared automatically by reading SCI1S1 with and then doing one of the following three things: • Write to the SCI data register (SCI1D) to transmit new data • Queue a preamble by changing TE from • Queue a break character by writing 1 to SBK in SCI1C2 Freescale Semiconductor Description Section 12.3.3.2, “Receiver Wakeup Section 12.3.2.1, “Send Break and Queued ...
Page 154
... Parity Error Flag — set at the same time as RDRF when parity is enabled ( and the parity bit in PF the received character does not agree with the expected parity value. To clear PF, read SCI1S1 and then read the SCI data register (SCI1D parity error. 1 Parity error. 154 Description MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
Page 155
... TxD Pin Direction in Single-Wire Mode — When the SCI is configured for single-wire half-duplex operation TXDIR (LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin. 0 TxD pin is an input in single-wire mode. 1 TxD pin is an output in single-wire mode. Freescale Semiconductor ...
Page 156
... Reads and writes of this register are also involved in the automatic flag clearing mechanisms for the SCI status flags Reset 0 0 156 Description Figure 12-10. SCI Data Register (SCI1D) MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. Freescale Semiconductor ...
Page 157
... For a Freescale Semiconductor SCI system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about ±4.5 percent for 8-bit data format and about ± ...
Page 158
... This action queues a break character to be sent as soon as the shifter is available. If SBK is still 1 when the queued break moves into the shifter (synchronized to the baud rate clock), an additional break character is queued. If the receiving device is another Freescale Semiconductor SCI, the break characters will be received all eight data bits and a framing error ( occurs. ...
Page 159
... At the end of a message the beginning of the next message, all receivers automatically force RWU all receivers wake up in time to look at the first character(s) of the next message. Freescale Semiconductor MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Serial Communications Interface (S08SCIV1) Section 12 ...
Page 160
... ISR anyway to check for receive errors, so the sequence is automatically satisfied. The IDLE status flag includes logic that prevents it from getting set repeatedly when the RxD1 line remains idle for an extended period of time. IDLE is cleared by reading SCI1S1 while IDLE = 1 and then reading 160 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
Page 161
... When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or single-wire mode (RSRC = 1). Loop mode is sometimes used to check software, independent of connections in the external system, to help isolate system problems. In this mode, the transmitter output is Freescale Semiconductor MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Serial Communications Interface (S08SCIV1) ...
Page 162
... TxD1 pin so an external device can send serial data to the receiver. When TXDIR = 1, the TxD1 pin is an output driven by the transmitter. In single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter. 162 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
Page 163
... High current drive 6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and rising edge is selected (KBEDGn = 1). Figure 13-1. MC9S08RC/RD/RE/RG Block Diagram Highlighting SPI Block and Pins Freescale Semiconductor INTERNAL BUS DEBUG MODULE (DBG) 8-BIT KEYBOARD ...
Page 164
... In this system, the master device has configured its SS1 pin as an optional slave select output. MASTER SPI SHIFTER CLOCK GENERATOR 164 MOSI1 MOSI1 MISO1 MISO1 SPSCK1 SPSCK1 SS1 SS1 Figure 13-2. SPI System Connections MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 SLAVE SPI SHIFTER Freescale Semiconductor ...
Page 165
... In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all MOSI pins together. Peripheral devices often use slightly different names for these pins. Freescale Semiconductor MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Serial Peripheral Interface (SPI) Module ...
Page 166
... MODE FAULT DETECTION <st-blue> <st-blue> <st-blue> <st-blue> <st-blue> Figure 13-3. SPI Module Block Diagram MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 PIN CONTROL <st-blue> <st-blue> MASTER CLOCK M SLAVE CLOCK S MASTER/ SLAVE <st-blue> <st-blue> SPI INTERRUPT REQUEST Freescale Semiconductor MOSI1 (MOMI) MISO1 (SISO) SPSCK1 SS1 ...
Page 167
... There is no indication for such an overrun condition so the application system designer must ensure that previous data has been read from the receive buffer before a new transfer is initiated. Freescale Semiconductor PRESCALER CLOCK RATE DIVIDER ...
Page 168
... SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST LSB FIRST MISO (SLAVE OUT) SS OUT (MASTER (SLAVE) 168 1 2 ... BIT 7 BIT 6 ... BIT 0 BIT 1 ... Figure 13-5. SPI Clock Formats (CPHA = 1) MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. BIT 2 BIT 1 BIT 0 BIT 5 BIT 6 BIT 7 Freescale Semiconductor ...
Page 169
... SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST BIT 7 LSB FIRST BIT 0 MISO (SLAVE OUT) SS OUT (MASTER (SLAVE) Freescale Semiconductor 2 ... 6 BIT 6 ... BIT 2 BIT 1 BIT 5 ... Figure 13-6. SPI Clock Formats (CPHA = 0) MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Serial Peripheral Interface (SPI) Module 7 ...
Page 170
... I/O pin. When the SPI is enabled as a master and MODFEN = 1, the slave select output enable bit determines whether this pin acts as the mode fault input (SSOE = the slave select output (SSOE = 1). 170 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
Page 171
... SPI registers. This section refers to registers and control bits only by their names, and a Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. Freescale Semiconductor Memory chapter of this data sheet for the absolute address MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 ...
Page 172
... First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer. 172 <st-blue> <st-blue> <st-blue> SPE SPTIE MSTR Formats,” for more details. Formats,” for more details. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. Bit 0 <st-blue> <st-blue> <st-blue> <st-blue> CPOL CPHA SSOE LSBFE Freescale Semiconductor ...
Page 173
... Mode fault function enabled, master SS1 pin acts as the mode fault input or the slave select output Mode fault function disabled, master SS1 pin reverts to general-purpose I/O not controlled by SPI. Freescale Semiconductor Table 13-1. SS1 Pin Function Master Mode General-purpose I/O (not SPI) ...
Page 174
... The output of this prescaler drives the input of the SPI baud rate divider (see 174 <st-blue> <st-blue> <st-blue> SPPR2 SPPR1 SPPR0 Unimplemented or Reserved Figure 13-4). MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. Bit 0 0 <st-blue> <st-blue> <st-blue> SPR2 SPR1 SPR0 Table 13-2. The Freescale Semiconductor ...
Page 175
... This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in input to this divider comes from the SPI baud rate prescaler (see divider is the SPI bit rate clock for master mode. SPR2:SPR1:SPR0 Freescale Semiconductor Table 13-2. SPI Baud Rate Prescaler Divisor Prescaler Divisor 0:0:0 ...
Page 176
... MSTR = 1, MODFEN = 1, and SSOE = 0; otherwise, MODF will never be set. MODF is cleared by reading MODF while then writing to SPI control register 1 (SPI1C1 Mode fault error detected mode fault error. 176 <st-blue> <st-blue> 0 SPTEF MODF Unimplemented or Reserved Figure 13-10. SPI Status Register (SPI1S) MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. Bit Freescale Semiconductor ...
Page 177
... Data may be read from SPI1D any time after SPRF is set and before another transfer is finished. Failure to read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition and the data from the new transfer is lost. Freescale Semiconductor 6 5 ...
Page 178
... Serial Peripheral Interface (SPI) Module 178 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
Page 179
... PTA[7:4] contain both pullup and pulldown devices. Pulldown enabled when KBI is enabled (KBIPEn = 1) and rising edge is selected (KBEDGn = 1). Figure 14-1. MC9S08RC/RD/RE/RG Block Diagram Highlighting ACMP Block and Pins Freescale Semiconductor INTERNAL BUS DEBUG MODULE (DBG) 8-BIT KEYBOARD ...
Page 180
... ACMP1+ pin is connected to the comparator non-inverting input if ACBGS is equal to logic 0, and the ACMP1– pin is connected to the inverting input of the comparator. 180 INTERNAL BUS ACBGS STATUS & CONTROL ACPE REGISTER + INTERRUPT CONTROL – MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 ACIE AC IRQ ACF Freescale Semiconductor ...
Page 181
... In stop3 mode, control and status register information is maintained and upon recovery normal ACMP function is available to the user. 14.4.4 Background Mode Operation When the microcontroller is in active background mode, the ACMP will continue to operate normally. Freescale Semiconductor MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Analog Comparator (ACMP) Block Description 181 ...
Page 182
... ACF bit. 00 Comparator output falling edge 01 Comparator output rising edge 10 Comparator output falling edge 11 Comparator output either rising or falling edge 182 5 4 ACO ACF ACIE 0 0 Table 14-1. ACMP1SC Field Descriptions Description MC9S08RC/RD/RE/RG Data Sheet, Rev. 1. ACMOD1 Freescale Semiconductor 0 ACMOD0 0 ...
Page 183
... Force breakpoints for any address access • Nine trigger modes: — A-only — — A then B — A AND B data (full mode) — A AND NOT B data (full mode) — Event-only B (store data) — A then event-only B (store data) Freescale Semiconductor MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 183 ...
Page 184
... This pin is also used to request a timed sync response pulse to allow a host development tool to determine the correct clock frequency for background debug serial communications. 184 2 GND BKGD 1 NO CONNECT 3 4 RESET NO CONNECT Figure 15-1. BDM Tool Connector MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 can be used to allow the pod to use DD Freescale Semiconductor ...
Page 185
... The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but asynchronous to the external host. The internal BDC clock signal is shown for reference in counting cycles. Freescale Semiconductor Details,” for more detail. ...
Page 186
... BDC CLOCK (TARGET MCU) HOST TRANSMIT 1 HOST TRANSMIT 0 SYNCHRONIZATION UNCERTAINTY PERCEIVED START OF BIT TIME Figure 15-2. BDC Host-to-Target Serial Bit Timing 186 10 CYCLES TARGET SENSES BIT LEVEL MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 EARLIEST START OF NEXT BIT Freescale Semiconductor ...
Page 187
... HOST DRIVE TO BKGD PIN TARGET MCU SPEEDUP PULSE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME BKGD PIN Figure 15-3. BDC Target-to-Host Serial Bit Timing (Logic 1) Freescale Semiconductor HIGH-IMPEDANCE R-C RISE 10 CYCLES 10 CYCLES HOST SAMPLES BKGD PIN MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Development Support HIGH-IMPEDANCE ...
Page 188
... TARGET MCU DRIVE AND SPEED-UP PULSE PERCEIVED START OF BIT TIME BKGD PIN Figure 15-4. BDM Target-to-Host Serial Bit Timing (Logic 0) 188 HIGH-IMPEDANCE 10 CYCLES 10 CYCLES HOST SAMPLES BKGD PIN MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 SPEEDUP PULSE EARLIEST START OF NEXT BIT Freescale Semiconductor ...
Page 189
... BDCSCR in the host-to-target direction (CONTROL) RBKP = 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint register) WBKP = 16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint register) Freescale Semiconductor to describe the coding structure of the BDC commands. MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Development Support 189 ...
Page 190
... Write accumulator (A) Write condition code register (CCR) Write program counter (PC) Write H and X register pair (H:X) Write stack pointer (SP) Increment H:X by one, then write memory byte located at H:X Increment H:X by one, then write memory byte located at H:X. Also report status. Freescale Semiconductor ...
Page 191
... The force/tag select (FTS) control bit in BDCSCR is used to select forced (FTS = 1) or tagged (FTS = 0) type breakpoints. The on-chip debug module (DBG) includes circuitry for two additional hardware breakpoints that are more flexible than the simple breakpoint in the BDC module. Freescale Semiconductor MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Development Support 191 ...
Page 192
... FIFO. Status bits indicate the number of words of valid information that are in the FIFO as data is stored into it trace run is manually halted by writing 0 to ARM before the FIFO is full (CNT = 1:0:0:0), the information is shifted by one position and 192 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
Page 193
... Freescale Semiconductor MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Development Support Section 15.3.5, “Trigger Modes” ...
Page 194
... RWA (RWB) value to be matched against R/W. The signal from the comparator with optional R/W qualification is used to request a CPU breakpoint if BRKEN = 1 and TAG determines whether the CPU request will be a tag request or a force request. 194 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
Page 195
... A and less than or equal to the value in comparator B at the same time. Outside Range (Address < Address > B) — A trigger occurs when the address is either less than the value in comparator A or greater than the value in comparator B. Freescale Semiconductor MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Development Support ...
Page 196
... WSF, and DVF) are read-only status indicators and can never be written by the WRITE_CONTROL serial BDC command. The clock switch (CLKSW) control bit may be read or written at any time. 196 Modes,” used to generate a hardware breakpoint request to the MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
Page 197
... Breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) 3 Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC CLKSW clock source. 0 Alternate BDC clock source 1 MCU bus clock Freescale Semiconductor 5 4 BKPTEN FTS CLKSW 0 0 ...
Page 198
... This register contains a single write-only control bit. A serial active background mode command such as WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are ignored. Reads always return 0x00. 198 Description Breakpoint.” MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...
Page 199
... ARM = 1. 15.4.3.4 Debug Comparator B Low Register (DBGCBL) This register contains compare value bits for the low-order eight bits of comparator B. This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1. Freescale Semiconductor ...
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... The information stored into the FIFO on reads of DBGFL (while the FIFO is not armed) is the address of the most-recently fetched opcode. 200 MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11 Freescale Semiconductor ...