MC9S08RE16FDE Freescale Semiconductor, MC9S08RE16FDE Datasheet - Page 50
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MC9S08RE16FDE
Manufacturer Part Number
MC9S08RE16FDE
Description
IC MCU 16K FLASH 1K RAM 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08RE16FDE
Core Processor
HCS08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
48-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
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Memory
Table 4-6
50
PRDIV8
DIV[5:0]
DIVLD
Field
5:0
7
6
Reset
W
R
shows the appropriate values for PRDIV8 and DIV5:DIV0 for selected bus frequencies.
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for FLASH.
1 FCDIV has been written since reset; erase and program operations enabled for FLASH.
Prescale (Divide) FLASH Clock by 8
0 Clock input to the FLASH clock divider is the bus rate clock.
1 Clock input to the FLASH clock divider is the bus rate clock divided by 8.
Divisor for FLASH Clock Divider — The FLASH clock divider divides the bus rate clock (or the bus rate clock
divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV5:DIV0 field plus one. The resulting frequency of the
internal FLASH clock must fall within the range of 200 kHz to 150 kHz for proper FLASH operations.
Program/erase timing pulses are one cycle of this internal FLASH clock, which corresponds to a range of 5 µs
to 6.7 µs. The automated programming logic uses an integer number of these pulses to complete an erase or
program operation. See
DIVLD
200 kHz
150 kHz
8 MHz
4 MHz
2 MHz
1 MHz
f
0
7
Bus
if PRDIV8 = 1 — f
= Unimplemented or Reserved
(Binary)
PRDIV8
if PRDIV8 = 0 — f
PRDIV8
Figure 4-5. FLASH Clock Divider Register (FCDIV)
0
0
0
0
0
0
6
0
Table 4-6. FLASH Clock Divider Settings
Equation 4-1
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Table 4-5. FCDIV Field Descriptions
DIV5:DIV0
(Decimal)
DIV5
FCLK
0
39
19
5
9
4
0
0
FCLK
and
= f
= f
Bus
Equation
Bus
DIV4
÷ (8 × ([DIV5:DIV0] + 1))
200 kHz
200 kHz
200 kHz
200 kHz
200 kHz
150 kHz
4
0
f
FCLK
Description
÷ ([DIV5:DIV0] + 1)
4-2.
DIV3
Program/Erase Timing Pulse
0
3
(5 µs Min, 6.7 µs Max)
DIV2
6.7 µs
5 µs
5 µs
5 µs
5 µs
5 µs
2
0
Freescale Semiconductor
DIV1
0
1
Eqn. 4-1
Eqn. 4-2
DIV0
0
0
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