M30800SAFP#D3 Renesas Electronics America, M30800SAFP#D3 Datasheet

Page 1

To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

Page 2

All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

Page 3

M32C/80 Group SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER 1. Overview The M32C/80 Group microcomputer is a single-chip control unit that utilizes high-performance silicon gate CMOS technology with the M32C/80 series CPU core. The M32C/80 Group is available in 100-pin plastic molded LQFP/QFP ...

Page 4

1.2 Performance Overview Table 1.1 lists performance overview of the M32C/80 Group. Table 1.1 M32C/80 Group Performance Item CPU Basic Instructions Minimum Instruction Execution Time Operating Mode Memory ...

Page 5

1.3 Block Diagram Figure 1.1 shows a block diagram of the M32C/80 Group microcomputer. 8 (1) Port P0 Peripheral Functions Timer (16 bits) Timer A: 5 channels Timer ...

Page 6

1.4 Product Information Table 1.2 lists the product information. Figure 1.2 shows the product numbering system. Table 1.2 M32C/80 Group ...

Page 7

1.5 Pin Assignment Figures 1.3 and 1.4 show pin assignments (top view ...

Page 8

...

Page 9

Table 1.3 Pin Characteristics Package Control Interrupt Pin No Port pins pins 100 ...

Page 10

Table 1.3 Pin Characteristics (Continued) Package Control Interrupt pin No Port pins pins ...

Page 11

1.6 Pin Description Table 1.4 Pin Description Signal name Pin name I/O type Power supply V V CC1, CC2 V SS Analog power AV CC supply input AV ...

Page 12

Table 1.4 Pin Description (Continued) Signal name Pin name I/O type Main clock input X IN Main clock X OUT output Sub clock input X CIN Sub clock ...

Page 13

Table 1.5 Pin Description (Continued) Signal name Pin name I/O type Reference V REF voltage input A/D converter ___________ AD TRG ANEX0 ANEX1 ...

Page 14

Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The register bank is comprised of 8 registers (R0, R1, R2, R3, A0, A1, SB and FB) ...

Page 15

2.1 General Registers 2.1.1 Data Registers (R0, R1, R2 and R3) R0, R1, R2 and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 ...

Page 16

2.1.8.5 Register Bank Select Flag (B) The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this ...

Page 17

Memory Figure 3.1 shows a memory map of the M32C/80 Group. The M32C/80 Group provides 16-Mbyte address space addressed from 000000 The fixed interrupt vectors are allocated ...

Page 18

Special Function Registers (SFRs) Address 0000 16 0001 16 0002 16 0003 16 0004 Processor Mode Register 16 0005 Processor Mode Register 1 16 0006 System Clock ...

Page 19

Address Register 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 Address Match Interrupt Register 6 16 003A ...

Page 20

Address 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 DMA0 Interrupt Control Register 16 0069 Timer B5 Interrupt Control ...

Page 21

Address 0090 UART0 Transmit /NACK Interrupt Control Register 16 0091 UART1/UART4 Bus Conflict Detect Interrupt Control Register 16 0092 UART1 Transmit/NACK Interrupt Control Register 16 0093 Key Input ...

Page 22

Address 00C0 16 00C1 16 00C2 16 00C3 16 00C4 16 00C5 16 00C6 16 00C7 16 00C8 16 00C9 16 00CA 16 00CB 16 00CC 16 00CD ...

Page 23

Address 00F0 Data Compare Register 00 16 00F1 Data Compare Register 01 16 00F2 Data Compare Register 02 16 00F3 Data Compare Register 03 16 00F4 Data Mask ...

Page 24

Address 0120 16 0121 16 0122 16 0123 16 0124 16 0125 16 0126 16 0127 16 0128 16 SI/O Receive Buffer Register 1 0129 16 012A Transmit ...

Page 25

Address 02B1 16 02B2 16 02B3 16 02B4 16 02B5 16 02B6 16 02B7 16 02B8 16 02B9 16 02BA 16 02BB 16 02BC 16 02BD 16 02BE ...

Page 26

Address 02E0 X/Y Control Register 16 02E1 16 02E2 16 02E3 16 02E4 UART1 Special Mode Register 4 16 02E5 UART1 Special Mode Register 3 16 02E6 UART1 ...

Page 27

Address 0310 16 Timer B3 Register 0311 16 0312 16 Timer B4 Register 0313 16 0314 16 Timer B5 Register 0315 16 0316 16 0317 16 0318 16 ...

Page 28

Address 0340 Count Start Flag 16 0341 Clock Prescaler Reset Flag 16 0342 One-Shot Start Flag 16 0343 Trigger Select Register 16 0344 Up/Down Flag 16 0345 16 ...

Page 29

Address 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 16 0378 DMA0 Request Source Select Register 16 0379 DMA1 Request Source ...

Page 30

Address 03A0 16 03A1 16 03A2 16 03A3 16 03A4 16 03A5 16 03A6 16 03A7 Function Select Register D1 16 03A8 16 03A9 16 03AA 16 03AB ...

Page 31

Address 03D0 16 03D1 16 03D2 16 03D3 16 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA Pull-Up Control Register 2 16 03DB ...

Page 32

Electrical Characteristics Table 5.1 Absolute Maximum Ratings ...

Page 33

Table 5.2 Recommended Operating Conditions ( =3.0V to 5.5V at Topr=– CC1 CC2 ...

Page 34

Table 5.2 Recommended Operating Conditions (Continued =3.0V to 5.5V at Topr=– CC1 CC2 ...

Page 35

Table 5.3 Electrical Characteristics (V =V =4.2 to 5.5V, V CC1 CC2 ...

Page 36

Table 5.4 A/D Conversion Characteristics (V o Topr=– ...

Page 37

Timing Requirements (V =V =4.2 to 5.5V, V CC1 CC2 Table 5.6 External Clock Input ...

Page 38

Timing Requirements (V =V =4.2 to 5.5V, V CC1 CC2 Table 5.8 Timer A Input (Count Source Input in Event Counter Mode ...

Page 39

Timing Requirements ( 4.2 to 5.5V, V CC1 CC2 Table 5.13 Timer B Input (Count Source Input in Event Counter Mode ...

Page 40

Switching Characteristics ( 4.2 to 5.5V, V CC1 CC2 Table 5.19 Memory Expansion Mode and Microprocessor Mode (when accessing external memory space ...

Page 41

Switching Characteristics (V = 4.2 to 5.5V Topr = – Table 5.20 Memory Expansion Mode and Microprocessor Mode (when accessing ...

Page 42

Figure 5 P10 Measurement Circuit Page ...

Page 43

Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space) [ Read Timing ] (1 +1 Bus Cycle) BCLK t d(BCLK-CS) 18ns.max CSi tcyc t d(BCLK-AD) ...

Page 44

Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus) [ Read Timing ] (2 +2 Bus Cycle) BCLK t d(BCLK-ALE) 18ns.max ...

Page 45

TAi Input IN TAi Input OUT TAi Input OUT (Counter increment/ decrement input) In event counter mode TAi Input IN (When counting on the falling edge) TAi Input ...

Page 46

Memory Expansion Mode and Microprocessor Mode BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input BCLK t su(HOLD–BCLK) ...

Page 47

Table 5.21 Electrical Characteristics (V f(BCLK)=24MH " " ...

Page 48

Table 5.22 A/D Conversion Characteristics (V at Topr = – ...

Page 49

Timing Requirements ( 3.0 to 3.6V, V CC1 CC2 Table 5.24 External Clock Input ...

Page 50

Timing Requirements ( 3.0 to 3.6V, V CC1 CC2 Table 5.26 Timer A Input (Count Source Input in Event Counter Mode ...

Page 51

Timing Requirements ( 3.0 to 3.6V, V CC1 CC Table 5.31 Timer B Input (Count Source Input in Event Counter Mode ...

Page 52

Switching Characteristics (V =V =3.0 to 3.6V, VSS = 0V at Topr = – CC1 CC2 Table 5.37 Memory Expansion Mode and Microprocessor Mode (when accessing ...

Page 53

Switching Characteristics ( 3.0 to 3.6V, VSS = 0V at Topr = – CC1 CC2 Table 5.38 Memory Expansion Mode and Microprocessor Mode ...

Page 54

Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space) [Read Timing Bus Cycles) BCLK t d(BCLK-CS) (1) 18ns.max CSi tcyc t d(BCLK-AD) ...

Page 55

Memory Expansion Mode and Microprocessor Mode (when accessing external memory space and using the multiplexed bus) [ Read Timing ] (2 +2 Bus Cycles) BCLK t d(BCLK-ALE) 18ns.max ...

Page 56

TAi Input IN TAi Input OUT TAi Input OUT (Counter increment/ decrement input) In event counter mode TAi Input IN (When counting on falling edge) TAi Input IN ...

Page 57

Memory Expansion Mode and Microprocessor Mode BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input BCLK t su(HOLD–BCLK) ...

Page 58

Package Dimensions JEITA Package Code RENESAS Code P-LQFP100-14x14-0.50 PLQP0100KB 100 1 Index mark JEITA Package Code RENESAS Code ...

Page 59

REVISION HISTORY Rev. Date Page – New Document 0.10 Sep Table 1.1.1 “CAN” deleted 0.11 Sep Table 1.1.1 0.12 Nov., 02 – 0.30 Aug Overview 1.2 Performance Outline 1.3 Block Diagram 1.5 Pin Assignments ...

Page 60

REVISION HISTORY Rev. Date Page Electrical Characteristics 30- • This capter added All pages Package code chnaged: 100P6Q-A to PLQP0100KB-A and 100P6S-A to PRQP0100JB-A 1.10 Nov., 05 Overview 1 • Note that the M32C/80 Group is ROMless device added 2 ...

Page 61

REVISION HISTORY Rev. Date Page 53 • Figure 5.7 V Description =V =3.3V Timing Diagram (2) Expression for tcyc added; CC1 CC2 notes 1 and 2 corrected A-3 M32C/80 Group Datasheet Summary ...

Page 62

Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...