M30280F6HP#D7 Renesas Electronics America, M30280F6HP#D7 Datasheet - Page 327

• Manufacturer Part Number: M30280F6HP#D7
• Description: MCU 3/5V 48K I-TEMP 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280F6HP#D7

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
R
R
1
e
E
. v
6
J
18.4.1 EW Mode 0
18.4.2 EW Mode 1
0
C
2
9
The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU
rewrite mode enabled) and is ready to accept software commands. EW mode 0 is selected by setting the
FMR11 bit in the FMR1 register to “0”.
To set the FMR01 bit to “1”, set to “1” after first writing “0”. The software commands control programming
and erasing. The FMR0 register or the status register indicates whether a programming or erasing opera-
tions is completed.
When entering the erase-suspend during the auto-erasing, set the FMR40 bit to “1” (erase-suspend
enabled) and the FMR41 bit to “1” (suspend request). After waiting for td(SR-ES) and verifying the
FMR46 bit is set to “1” (auto-erase stop), access to the user ROM area. When setting the FMR41 bit to “0”
(erase restart), auto-erasing is restarted.
EW mode 1 is selected by setting the FMR11 bit to “1” after the FMR01 bit is set to “1” (set to “1” after first
writing “0”).
The FMR0 register indicates whether or not a programming or an erasing operation is completed. Read
status register cannot be read in EW mode 1.
When an erase/program command is initiated, the CPU halts all program execution until the command
operation is completed or erase-suspend request is generated.
When enabling an erase-suspend function, set the FMR40 bit to “1” (erase suspend enabled) and ex-
ecute block erase commands. Also, the interrupt to transfer to erase-suspend must be set enabled pre-
liminarily. When entering erase-suspend after td(SR-ES) from an interrupt is requested, interrupts can be
accepted.
When an interrupt request is generated, the FMR41 bit is automatically set to “1” (suspend request) and
an auto-erasing is suspended. If an auto-erasing has not completed (when the FMR00 bit is “0”) after an
interrupt process is completed, set the FMR41 bit to “0” (erase restart) and execute block erase com-
mands again.
2 /
0 .
B
0
8
0
0
G
4
J
7
a
o r
0 -
. n
u
2
3
p
0
, 1
0
(
M
2
0
1
0
6
7
C
2 /
page 305
, 8
M
1
6
C
2 /
f o
8
3
) B
8
5
18. Flash Memory Version