MC908GR60AMFAE Freescale Semiconductor, MC908GR60AMFAE Datasheet - Page 270

• Manufacturer Part Number: MC908GR60AMFAE
• Description: IC MCU 8BIT 60K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR60AMFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Development Support
Enter monitor mode with pin configuration shown in
rising edge of RST latches monitor mode. Once monitor mode is latched, the levels on the port pins
except PTA0 can change.
Once out of reset, the MCU waits for the host to send eight security bytes (see
security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to
receive a command.
270
Function
[Pin No.]
Monitor
Monitor
MON08
Normal
Forced
Mode
1. PTA0 must have a pullup resistor to V
2. Communication speed in the table is an example to obtain a baud rate of 7200. Baud rate using external oscillator is bus
3. External clock is a 4.0 MHz or 8.0 MHz crystal on OSC1 and OSC2 or a canned oscillator on OSC1.
4. X = don’t care
5. MON08 pin refers to P&E Microcomputer Systems’ MON08-Cyclone 2 by 8-pin connector.
User
frequency / 278.
V
V
V
V
V
IRQ
V
V
[6]
or
or
TST
TST
TST
DD
SS
DD
SS
OSC1
V
NC
NC
NC
NC
NC
NC
DD
V
V
V
RST
RST
V
V
V
V
[4]
or
or
or
TST
TST
TST
DD
DD
DD
DD
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Table 19-1. Monitor Mode Signal Requirements and Options
Vector
(blank)
Reset
$FF
$FF
Not
11
13
15
—
X
X
1
3
5
7
9
Communication
PTA0
COM
[8]
10
12
14
16
X
1
1
1
2
4
6
8
Serial
DD
PTA1
SSEL
PTB0
PTB1
PTB4
PTA0
PTA1
GND
RST
IRQ
[10]
in monitor mode.
X
0
0
0
MOD0
PTB0 PTB1
[12]
Selection
X
X
1
1
Mode
MOD1
[14]
X
X
Table 19-1
0
0
Divider
PTB4
DIV4
[16]
X
X
0
1
by pulling RST low and then high. The
OFF Disabled 4.0 MHz
OFF Disabled 8.0 MHz
OFF Disabled 8.0 MHz
PLL
—
X
Enabled
COP
—
External
19.3.2
Clock
OSC1
[13]
X
Freescale Semiconductor
Communication
Security). After the
Frequency
Speed
2.0 MHz
2.0 MHz
2.0 MHz
Bus
—
X
Baud
7200
7200
7200
Rate
—
X