MC68HC908QY1MDTE Freescale Semiconductor, MC68HC908QY1MDTE Datasheet - Page 77
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MC68HC908QY1MDTE
Manufacturer Part Number
MC68HC908QY1MDTE
Description
IC MCU 1.5K FLASH 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908QY4MDWER.pdf
(184 pages)
Specifications of MC68HC908QY1MDTE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
16-TSSOP
Processor Series
HC08Q
Core
HC08
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
13
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
- Current page: 77 of 184
- Download datasheet (2Mb)
8.7.1 IRQ Input Pins (IRQ)
The IRQ pin provides a maskable external interrupt source. The IRQ pin contains an internal pullup
device.
8.8 Registers
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. See
Chapter 5 Configuration Register
The INTSCR has the following functions:
IRQF — IRQ Flag
ACK — IRQ Interrupt Request Acknowledge Bit
IMASK — IRQ Interrupt Mask Bit
MODE — IRQ Edge/Level Select Bit
Freescale Semiconductor
•
•
•
•
This read-only status bit is set when the IRQ interrupt is pending.
Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads as 0.
Writing a 1 to this read/write bit disables the IRQ interrupt request.
This read/write bit controls the triggering sensitivity of the IRQ pin.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
1 = IRQ interrupt request disabled
0 = IRQ interrupt request enabled
1 = IRQ interrupt request on falling edges and low levels
0 = IRQ interrupt request on falling edges only
Shows the state of the IRQ flag
Clears the IRQ latch
Masks the IRQ interrupt request
Controls triggering sensitivity of the IRQ interrupt pin
Address: $001D
Reset:
Read:
Write:
Figure 8-3. IRQ Status and Control Register (INTSCR)
Bit 7
0
0
= Unimplemented
MC68HC908QY/QT Family Data Sheet, Rev. 6
(CONFIG).
6
0
0
5
0
0
4
0
0
IRQF
3
0
ACK
2
0
0
IMASK
1
0
MODE
Bit 0
0
Registers
77
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