C8051F330D Silicon Laboratories Inc, C8051F330D Datasheet - Page 120
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C8051F330D
Manufacturer Part Number
C8051F330D
Description
IC 8051 MCU 8K FLASH 20DIP
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Datasheet
1.C8051F330R.pdf
(208 pages)
Specifications of C8051F330D
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1155
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- Download datasheet (4Mb)
C8051F330/1, C8051F330D
14.3. General Purpose Port I/O
Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for
general purpose I/O. Ports2-0 are accessed through corresponding special function registers (SFRs) that
are both byte addressable and bit addressable. When writing to a Port, the value written to the SFR is
latched to maintain the output data value at each pin. When reading, the logic levels of the Port's input pins
are returned regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the
Crossbar, the Port register can always read its corresponding Port I/O pin). The exception to this is the
execution of the read-modify-write instructions that target a Port Latch register as the destination. The
read-modify-write instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL,
INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For
these instructions, the value of the register (not the pin) is read, modified, and written back to the SFR.
120
Bits7-0:
Bits7-0:
P0.7
R/W
R/W
Bit7
Bit7
P0.[7:0]
Write - Output appears on I/O pins per Crossbar Registers.
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P0MDOUT.n bit = 0).
Read - Always reads ‘0’ if selected as analog input in register P0MDIN. Directly reads Port
pin when configured as digital input.
0: P0.n pin is logic low.
1: P0.n pin is logic high.
Analog Input Configuration Bits for P0.7-P0.0 (respectively).
Port pins configured as analog inputs have their weak pull-up, digital driver, and digital
receiver disabled.
0: Corresponding P0.n pin is configured as an analog input.
1: Corresponding P0.n pin is not configured as an analog input.
P0.6
R/W
R/W
Bit6
Bit6
Figure 14.8. P0MDIN: Port0 Input Mode Register
P0.5
R/W
R/W
Bit5
Bit5
Figure 14.7. P0: Port0 Register
P0.4
R/W
R/W
Bit4
Bit4
Rev. 1.2
P0.3
R/W
R/W
Bit3
Bit3
P0.2
R/W
R/W
Bit2
Bit2
P0.1
R/W
R/W
Bit1
Bit1
(bit addressable)
P0.0
R/W
R/W
Bit0
Bit0
SFR Address:
SFR Address:
Reset Value
Reset Value
11111111
11111111
0x80
0xF1
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