C8051F312 Silicon Laboratories Inc, C8051F312 Datasheet - Page 8
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C8051F312
Manufacturer Part Number
C8051F312
Description
IC 8051 MCU 8K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F31xr
Specifications of C8051F312
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
29
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 21x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1151
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F312
Manufacturer:
SILICON
Quantity:
850
Company:
Part Number:
C8051F312
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F312-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F312-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051F310/1/2/3/4/5/6/7
7. Comparators
8. CIP-51 Microcontroller
9. Reset Sources
10. Flash Memory
11. External RAM
12. Oscillators
13. Port Input/Output
14. SMBus
15. UART0
16. Enhanced Serial Peripheral Interface (SPI0)
8
Figure 7.1. Comparator0 Functional Block Diagram ................................................ 69
Figure 7.2. Comparator1 Functional Block Diagram ................................................ 70
Figure 7.3. Comparator Hysteresis Plot ................................................................... 71
Figure 8.1. CIP-51 Block Diagram............................................................................ 79
Figure 8.2. Memory Map .......................................................................................... 85
Figure 9.1. Reset Sources...................................................................................... 105
Figure 9.2. Power-On and V
Figure 10.1. Flash Program Memory Map.............................................................. 113
Figure 12.1. Oscillator Diagram.............................................................................. 121
Figure 12.2. 32.768 kHz External Crystal Example................................................ 126
Figure 13.1. Port I/O Functional Block Diagram ..................................................... 129
Figure 13.2. Port I/O Cell Block Diagram ............................................................... 130
Figure 13.3. Crossbar Priority Decoder with No Pins Skipped ............................... 131
Figure 13.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 132
Figure 14.1. SMBus Block Diagram ....................................................................... 145
Figure 14.2. Typical SMBus Configuration ............................................................. 146
Figure 14.3. SMBus Transaction ............................................................................ 147
Figure 14.4. Typical SMBus SCL Generation......................................................... 151
Figure 14.5. Typical Master Transmitter Sequence................................................ 157
Figure 14.6. Typical Master Receiver Sequence.................................................... 158
Figure 14.7. Typical Slave Receiver Sequence...................................................... 159
Figure 14.8. Typical Slave Transmitter Sequence.................................................. 160
Figure 15.1. UART0 Block Diagram ....................................................................... 163
Figure 15.2. UART0 Baud Rate Logic .................................................................... 164
Figure 15.3. UART Interconnect Diagram .............................................................. 165
Figure 15.4. 8-Bit UART Timing Diagram............................................................... 165
Figure 15.5. 9-Bit UART Timing Diagram............................................................... 166
Figure 15.6. UART Multi-Processor Mode Interconnect Diagram .......................... 167
Figure 16.1. SPI Block Diagram ............................................................................. 173
Figure 16.2. Multiple-Master Mode Connection Diagram ....................................... 176
Figure 16.3. 3-Wire Single Master and Slave Mode Connection Diagram ............. 176
Figure 16.4. 4-Wire Single Master and Slave Mode Connection Diagram ............. 176
Figure 16.5. Master Mode Data/Clock Timing ........................................................ 178
Figure 16.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 179
Figure 16.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 179
DD
Monitor Reset Timing ........................................... 106
Rev. 1.7