C8051F220 Silicon Laboratories Inc, C8051F220 Datasheet - Page 118

• Manufacturer Part Number: C8051F220
• Description: IC 8051 MCU 8K FLASH 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F2xxr

Specifications of C8051F220

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 32x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

C8051F2xx
16.1. UART Operational Modes
The UART provides four operating modes (one synchronous and three asynchronous) selected by setting
configuration bits in the SCON register. These four modes offer different baud rates and communication
protocols. The four modes are summarized in Table 16.1 below. Detailed descriptions follow.
16.1.1. Mode 0: Synchronous Mode
Mode 0 provides synchronous, half-duplex communication. Serial data is transmitted and received on the
RX pin. The TX pin provides the shift clock for both transmit and receive. The MCU must be the master
since it generates the shift clock for transmission in both directions (see the interconnect diagram in
Figure 16.2).
Eight data bits are transmitted/received, LSB first (see the timing diagram in Figure 16.3). Data transmis-
sion begins when an instruction writes a data byte to the SBUF register. The TI Transmit Interrupt Flag
(SCON.1) is set at the end of the eighth bit time. Data reception begins when the REN Receive Enable bit
(SCON.4) is set to logic 1 and the RI Receive Interrupt Flag (SCON.0) is cleared. One cycle after the
eighth bit is shifted in, the RI flag is set and reception stops until software clears the RI bit. An interrupt will
occur if enabled when either TI or RI are set.
The Mode 0 baud rate is system clock frequency divided by twelve.
118
Mode
0
1
2
3
Synchronization
Asynchronous
Asynchronous
Asynchronous
Synchronous
RX (data out)
RX (data in)
TX (clk out)
TX (clk out)
Figure 16.3. UART Mode 0 Timing Diagram
Figure 16.2. UART Mode 0 Interconnect
C8051Fxxx
Table 16.1. UART Modes
D0
D0
Timer 1 or Timer 2 Overflow
Timer 1 or Timer 2 Overflow
SYSCLK/32 or SYSCLK/64
D1
TX
RX
D1
Baud Clock
MODE 0 TRANSMIT
SYSCLK/12
MODE 0 RECEIVE
Rev. 1.6
D2
D2
D3
D3
CLK
DATA
D4
8 Extra Outputs
D4
D5
Reg.
Shift
D5
Data Bits
D6
D6
8
8
9
9
D7
D7
Start/Stop Bits
1 Start, 1 Stop
1 Start, 1 Stop
1 Start, 1 Stop
None