MC68HC908GT16CB Freescale Semiconductor, MC68HC908GT16CB Datasheet - Page 167

no-image

MC68HC908GT16CB

Manufacturer Part Number
MC68HC908GT16CB
Description
IC MCU 16K FLASH 8MHZ SPI 42-DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908GT16CB

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
36
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908GT16CB
Manufacturer:
FREESCALE
Quantity:
92
14.8.3 ESCI Control Register 3
ESCI control register 3 (SCC3):
R8 — Received Bit 8
T8 — Transmitted Bit 8
ORIE — Receiver Overrun Interrupt Enable Bit
NEIE — Receiver Noise Error Interrupt Enable Bit
FEIE — Receiver Framing Error Interrupt Enable Bit
PEIE — Receiver Parity Error Interrupt Enable Bit
Freescale Semiconductor
When the ESCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received
character. R8 is received at the same time that the SCDR receives the other 8 bits.
When the ESCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect
on the R8 bit.
When the ESCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted
character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset clears the T8 bit.
This read/write bit enables ESCI error CPU interrupt requests generated by the receiver overrun bit,
OR. Reset clears ORIE.
This read/write bit enables ESCI error CPU interrupt requests generated by the noise error bit, NE.
Reset clears NEIE.
This read/write bit enables ESCI error CPU interrupt requests generated by the framing error bit, FE.
Reset clears FEIE.
This read/write bit enables ESCI receiver CPU interrupt requests generated by the parity error bit, PE.
Reset clears PEIE.
1 = ESCI error CPU interrupt requests from OR bit enabled
0 = ESCI error CPU interrupt requests from OR bit disabled
1 = ESCI error CPU interrupt requests from NE bit enabled
0 = ESCI error CPU interrupt requests from NE bit disabled
1 = ESCI error CPU interrupt requests from FE bit enabled
0 = ESCI error CPU interrupt requests from FE bit disabled
1 = ESCI error CPU interrupt requests from PE bit enabled
0 = ESCI error CPU interrupt requests from PE bit disabled
Stores the ninth ESCI data bit received and the ninth ESCI data bit to be transmitted.
Enables these interrupts:
Receiver overrun
Noise error
Framing error
Parity error
Address:
Reset:
Read:
Write:
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
$0015
Bit 7
R8
U
Figure 14-12. ESCI Control Register 3 (SCC3)
= Unimplemented
T8
6
0
R
5
0
R
R
4
0
= Reserved
ORIE
3
0
U = Unaffected
NEIE
2
0
FEIE
1
0
PEIE
Bit 0
0
I/O Registers
167

Related parts for MC68HC908GT16CB