COP8SAB728M8 National Semiconductor, COP8SAB728M8 Datasheet - Page 45
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COP8SAB728M8
Manufacturer Part Number
COP8SAB728M8
Description
IC MCU OTP 8BIT 2K POR 28-SOIC
Manufacturer
National Semiconductor
Series
COP8™ 8SAr
Datasheet
1.COP8-PGMA-28CSP.pdf
(60 pages)
Specifications of COP8SAB728M8
Core Processor
COP8
Core Size
8-Bit
Speed
10MHz
Connectivity
Microwire/Plus (SPI)
Peripherals
POR, PWM, WDT
Number Of I /o
24
Program Memory Size
2KB (2K x 8)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
*COP8SAB728M8
13.0 Instruction Set
13.7 INSTRUCTION EXECUTION TIME
Most instructions are single byte (with immediate addressing
mode instructions taking two bytes).
Most single byte instructions take one cycle time to execute.
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped
instruction opcode.
See the BYTES and CYCLES per INSTRUCTION table for
details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles for
each instruction in the format of byte/cycle.
Arithmetic and Logic Instructions
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND
Addr.
Addr.
[B]
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
Jump SubRoutine Long
Jump SubRoutine
Jump InDirect
RETurn from subroutine
RETurn and SKip
RETurn from Interrupt
Generate an Interrupt
No OPeration
Direct
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
1/3
3/4
3/4
3/4
(Continued)
Immed.
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
45
Instructions Using A & C
Transfer of Control Instructions
CLRA
INCA
DECA
LAID
DCORA
RRCA
RLCA
SWAPA
SC
RC
IFC
IFNC
PUSHA
POPA
ANDSZ
JMPL
JMP
JP
JSRL
JSR
JID
VIS
RET
RETSK
RETI
INTR
NOP
[SP] PL, [SP−1] PU,SP−2, PC ii
[SP] PL, [SP−1] PU,SP−2, PC9…0 i
PL ROM (PU,A)
SP + 2, PL [SP], PU [SP−1]
SP + 2, PL [SP],PU [SP−1],
skip next instruction
SP + 2, PL
[SP] PL, [SP−1] PU, SP−2, PC 0FF
PC PC + 1
[SP],PU [SP−1],GIE 1
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2
3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5
1/7
1/1
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