MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 70
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MC68HC711E20CFN2
Manufacturer Part Number
MC68HC711E20CFN2
Description
IC MCU 20K 2MHZ OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Specifications of MC68HC711E20CFN2
Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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4.4 Opcodes and Operands
The M68HC11 Family of microcontrollers uses 8-bit opcodes. Each opcode identifies a particular
instruction and associated addressing mode to the CPU. Several opcodes are required to provide each
instruction with a range of addressing capabilities. Only 256 opcodes would be available if the range of
values were restricted to the number able to be expressed in 8-bit binary numbers.
A 4-page opcode map has been implemented to expand the number of instructions. An additional byte,
called a prebyte, directs the processor from page 0 of the opcode map to one of the other three pages.
As its name implies, the additional byte precedes the opcode.
A complete instruction consists of a prebyte, if any, an opcode, and zero, one, two, or three operands.
The operands contain information the CPU needs for executing the instruction. Complete instructions can
be from one to five bytes long.
4.5 Addressing Modes
Six addressing modes can be used to access memory:
These modes are detailed in the following paragraphs. All modes except inherent mode use an effective
address. The effective address is the memory address from which the argument is fetched or stored or
the address from which execution is to proceed. The effective address can be specified within an
instruction, or it can be calculated.
4.5.1 Immediate
In the immediate addressing mode, an argument is contained in the byte(s) immediately following the
opcode. The number of bytes following the opcode matches the size of the register or memory location
being operated on. There are 2-, 3-, and 4- (if prebyte is required) byte immediate instructions. The
effective address is the address of the byte following the instruction.
4.5.2 Direct
In the direct addressing mode, the low-order byte of the operand address is contained in a single byte
following the opcode, and the high-order byte of the address is assumed to be $00. Addresses $00–$FF
are thus accessed directly, using 2-byte instructions. Execution time is reduced by eliminating the
additional memory access required for the high-order address byte. In most applications, this
256-byte area is reserved for frequently referenced data. In M68HC11 MCUs, the memory map can be
configured for combinations of internal registers, RAM, or external memory to occupy these addresses.
70
Central Processor Unit (CPU)
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Immediate
Direct
Extended
Indexed
Inherent
Relative
M68HC11E Family Data Sheet, Rev. 5.1
Freescale Semiconductor
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