MC68HC711E20CFN2 Freescale Semiconductor, MC68HC711E20CFN2 Datasheet - Page 18

• Manufacturer Part Number: MC68HC711E20CFN2
• Description: IC MCU 20K 2MHZ OTP 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E20CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

List of Figures
Technical Data
18
Figure
4-13
4-14
4-15
4-16
4-17
5-1
5-2
5-3
5-4
5-5
5-6
5-7
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
7-1
7-2
7-3
7-4
7-5
7-6
7-7
System Configuration Options Register (OPTION) . . . . . . . . 91
Block Protect Register (BPROT) . . . . . . . . . . . . . . . . . . . . . . 99
Parallel I/O Control Register (PIOC). . . . . . . . . . . . . . . . . . .141
EPROM and EEPROM Programming
MC68HC711E20 EPROM Programming
EPROM and EEPROM Programming
Arm/Reset COP Timer Circuitry Register (COPRST). . . . . . 111
System Configuration Options Register (OPTION) . . . . . . . 112
Configuration Control Register (CONFIG) . . . . . . . . . . . . . . 113
Highest Priority I-Bit Interrupt
Processing Flow Out of Reset . . . . . . . . . . . . . . . . . . . . . . .125
Interrupt Priority Resolution . . . . . . . . . . . . . . . . . . . . . . . . . 127
Interrupt Source Resolution Within SCI . . . . . . . . . . . . . . . . 129
Port A Data Register (PORTA). . . . . . . . . . . . . . . . . . . . . . .134
Pulse Accumulator Control Register (PACTL) . . . . . . . . . . . 135
Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . .136
Port C Data Register (PORTC) . . . . . . . . . . . . . . . . . . . . . . 136
Port C Latched Register (PORTCL) . . . . . . . . . . . . . . . . . . .137
Port C Data Direction Register (DDRC) . . . . . . . . . . . . . . . . 137
Port D Data Register (PORTD) . . . . . . . . . . . . . . . . . . . . . . 138
Port D Data Direction Register (DDRD) . . . . . . . . . . . . . . . . 138
Port E Data Register (PORTE). . . . . . . . . . . . . . . . . . . . . . .139
SCI Transmitter Block Diagram . . . . . . . . . . . . . . . . . . . . . . 147
SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 149
Serial Communications Data Register (SCDR) . . . . . . . . . . 152
Serial Communications Control Register 1 (SCCR1) . . . . . . 153
Serial Communications Control Register 2 (SCCR2) . . . . . . 154
Serial Communications Status Register (SCSR) . . . . . . . . .155
Baud Rate Register (BAUD). . . . . . . . . . . . . . . . . . . . . . . . . 157
Control Register (PPROG) . . . . . . . . . . . . . . . . . . . . . . . .95
Control Register (EPROG) . . . . . . . . . . . . . . . . . . . . . . . .96
Control Register (PPROG) . . . . . . . . . . . . . . . . . . . . . . .101
and Miscellaneous Register (HPRIO) . . . . . . . . . . . . . . . 119
List of Figures
Title
M68HC11E Family — Rev. 3.2
MOTOROLA
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