MC68HC908MR32CFU Freescale Semiconductor, MC68HC908MR32CFU Datasheet - Page 151
MC68HC908MR32CFU
Manufacturer Part Number
MC68HC908MR32CFU
Description
IC MCU 8MHZ 32K FLASH 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908MR16CFUE.pdf
(282 pages)
Specifications of MC68HC908MR32CFU
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
44
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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FMODE4 —Fault Mode Selection for Fault Pin 4 Bit (automatic versus manual mode)
FINT3 — Fault 3 Interrupt Enable Bit
FMODE3 —Fault Mode Selection for Fault Pin 3 Bit (automatic versus manual mode)
FINT2 — Fault 2 Interrupt Enable Bit
FMODE2 —Fault Mode Selection for Fault Pin 2 Bit
(automatic versus manual mode)
FINT1 — Fault 1 Interrupt Enable Bit
FMODE1 —Fault Mode Selection for Fault Pin 1 Bit (automatic versus manual mode)
Freescale Semiconductor
This read/write bit allows the user to select between automatic and manual mode faults. For further
descriptions of each mode, see
This read/write bit allows the CPU interrupt caused by faults on fault pin 3 to be enabled. The fault
protection circuitry is independent of this bit and will always be active. If a fault is detected, the PWM
pins will still be disabled according to the disable mapping register.
This read/write bit allows the user to select between automatic and manual mode faults. For further
descriptions of each mode, see
This read/write bit allows the CPU interrupt caused by faults on fault pin 2 to be enabled. The fault
protection circuitry is independent of this bit and will always be active. If a fault is detected, the PWM
pins will still be disabled according to the disable mapping register.
This read/write bit allows the user to select between automatic and manual mode faults. For further
descriptions of each mode, see
This read/write bit allows the CPU interrupt caused by faults on fault pin 1 to be enabled. The fault
protection circuitry is independent of this bit and will always be active. If a fault is detected, the PWM
pins will still be disabled according to the disable mapping register.
This read/write bit allows the user to select between automatic and manual mode faults. For further
descriptions of each mode, see
1 = Automatic mode
0 = Manual mode
1 = Fault pin 3 will cause CPU interrupts.
0 = Fault pin 3 will not cause CPU interrupts.
1 = Automatic mode
0 = Manual mode
1 = Fault pin 2 will cause CPU interrupts.
0 = Fault pin 2 will not cause CPU interrupts.
1 = Automatic mode
0 = Manual mode
1 = Fault pin 1 will cause CPU interrupts.
0 = Fault pin 1 will not cause CPU interrupts.
1 = Automatic mode
0 = Manual mode
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
12.6 Fault
12.6 Fault
12.6 Fault
12.6 Fault
Protection.
Protection.
Protection.
Protection.
Control Logic Block
151
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