W78E051B40DL Nuvoton Technology Corporation of America, W78E051B40DL Datasheet - Page 12

• Manufacturer Part Number: W78E051B40DL
• Description: IC MCU 8-BIT 4K FLASH 40-DIP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W78r

Specifications of W78E051B40DL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

6.7.7
This operation allows parallel erasing or programming of multiple chips with different data. When
P3.6( CE ) = V
except for the P3.6 and P3.7 pins, the individual chips may have common inputs.
Notes:
7. SECURITY BITS
During the programmer operation mode, the Flash EPROM can be programmed and verified
repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be protected. The
protection of Flash EPROM and those operations on it are described below. The W78E51B has a
Special Setting Register, the Security Register, which can be accessed in normal mode. The register
can only be accessed from the Flash EPROM operation mode. Those bits of the Security Registers
can not be changed once they have been programmed from high to low. They can only be reset
through erase-all operation. The Security Register is addressed in the Flash EPROM operation mode
by address #0FFFFh.
Read
Output Disable
Program
Program
Verify
Erase
Erase Verify
Program/Erase
Inhibit
OPERATIONS
1. All these operations happen in RST = V
2. V
3. The program verify operation follows behind the program operation.
4. This erase operation will erase all the on-chip Flash EPROM cells and the Security bits.
5. The erase verify operation follows behind the erase operation.
Program/Erase Inhibit Operation
CP
= 12.5V, VEP = 14.5V, V
IH
, P3.7( OE ) = V
CTRL)
P3.0
(A9
X
0
0
0
0
1
1
CTRL)
(A13
P3.1
0
0
0
0
0
0
0
IH
= V
CTRL)
IH
(A14
P3.2
DD
0
0
0
0
0
0
0
, erasing or programming of non-targeted chips is inhibited. So,
, V
IH
IL
, ALE = V
= Vss.
CTRL)
P3.3
(OE
0
0
0
0
0
0
0
IL
- 12 -
and PSEN = V
(
P3.6
CE
0
0
0
1
0
1
1
)
(
P3.7
OE
0
1
1
0
1
0
1
IH
)
.
(V
V
V
V
V
V
V
EA
CP
1
1
PP
CP
CP
EP
EP
EP
/
)
(A15..A0)
others: X
Address
Address
Address
Address
P2, P1
A0:0,
X
X
Data Out
Data Out
Data Out
W78E51B
(D7..D0)
Data In
Data In
0FFH
Hi-Z
P0
X
NOTE
@3
@4
@5