ZGP323LEH2008G Zilog, ZGP323LEH2008G Datasheet - Page 59

• Manufacturer Part Number: ZGP323LEH2008G
• Description: IC Z8 GP MCU 8K OTP 20SSOP
• Manufacturer: Zilog
• Series: Z8® GP™r

Specifications of ZGP323LEH2008G

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: HLVD, POR, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: OTP
• Ram Size: 237 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4528; ZGP323LEH2008G

PS023709-0208
Watchdog Timer Mode Register (WDTMR)
The Watchdog Timer (WDT) is a retriggerable one-shot timer that resets the Z8
reaches its terminal count. The WDT must initially be enabled by executing the WDT
instruction. On subsequent executions of the WDT instruction, the WDT is refreshed. The
WDT circuit is driven by an on-board RC-oscillator. The WDT instruction affects the Zero
(Z), Sign (S), and Overflow (V) flags.
The POR clock source the internal RC-oscillator. Bits 0 and 1 of the WDT register control
a tap circuit that determines the minimum timeout period. Bit 2 determines whether the
WDT is active during HALT, and Bit 3 determines WDT activity during Stop. Bits 4
through 7 are reserved
processor cycles (120 XTAL clocks) from the execution of the first instruction after
Power-On-Reset, Watchdog Reset, or a Stop Mode Recovery
the register cannot be modified by any means (intentional or otherwise). The WDTMR
cannot be read. The register is located in Bank F of the Expanded Register Group at
address location
WDTMR(0F)0Fh
WDT Time Select (D0, D1)
This bit selects the WDT time period. It is configured as indicated in
D7
* Default setting after reset.
Figure 35. Watchdog Timer Mode Register (Write Only)
D6
D5
0Fh
D4
. It is organized as shown in
D3
(Figure
D2
35). This register is accessible only during the first 60
D1
D0
Figure
WDT TAP INT RC OSC
00
01*
10
11
WDT During HALT
0 OFF
1 ON *
WDT During Stop
0 OFF
1 ON *
Reserved (Must be 0)
35.
20 ms min.
80 ms min.
10 ms min.
(Figure
5 ms min.
Product Specification
34). After this point,
Table
Functional Description
15.

ZGP323L
CPU if it
55