CY8C25122-24PXI Cypress Semiconductor Corp, CY8C25122-24PXI Datasheet - Page 133

• Manufacturer Part Number: CY8C25122-24PXI
• Description: IC MCU 4K FLASH 256B 8-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ CY8C25xxxr

Specifications of CY8C25122-24PXI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.25 V
• Data Converters: A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.2.6
The following table lists guaranteed maximum and mini-
mum specifications for the voltage and temperature
ranges, 5V +/- 5% and -40°C <= TA <= 85°C. The guar-
anteed specifications are measured through the Analog
Continuous Time PSoC blocks. The bias levels for
AGND refer to the bias of the Analog Continuous Time
PSoC block. The bias levels for RefHi and RefLo refer to
Table 111:
September 5, 2002
Symbol
AGND = Vcc/2
AGND = 2*BandGap
AGND = P2[4] (P2[4] = Vcc/2)
AGND Column to Column Variation (AGND=Vcc/
2)
REFHI = Vcc/2 + BandGap
REFHI = 3*BandGap
REFHI = 2*BandGap + P2[6] (P2[6] = 1.3V)
REFHI = P2[4] + BandGap (P2[4] = Vcc/2)
REFHI = P2[4] + P2[6] (P2[4] = Vcc/2, P2[6] =
1.3V)
REFLO = Vcc/2 – BandGap
REFLO = BandGap
REFLO = 2*BandGap - P2[6] (P2[6] = 1.3V)
REFLO = P2[4] – BandGap (P2[4] = Vcc/2)
REFLO = P2[4]-P2[6] (P2[4] = Vcc/2, P2[6] =
1.3V)
CT Block Bias = High
CT Block Bias = High
CT Block Bias = High
CT Block Bias = High
Ref Control Bias = High
Ref Control Bias = High
Ref Control Bias = High
Ref Control Bias = High
Ref Control Bias = High
Ref Control Bias = High
Ref Control Bias = High
Ref Control Bias = High
Ref Control Bias = High
Ref Control Bias = High
DC Analog Reference Specifications
5V DC Analog Reference Specifications
1
5V DC Analog Reference Specifications
1
1
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
1
the Analog Reference Control Register. The limits stated
for AGND include the offset error of the AGND buffer
local to the Analog Continuous Time PSoC block. Typical
parameters apply to 5V at 25C and are for design guid-
ance only. (3.3V replaces 5V for the 3.3V DC Analog
Reference Specifications.)
V
2*BG - 0.043
P24 - 0.013
-0.034
V
3*BG - 0.112
2*BG+P2[6] -
0.113
P2[4]+BG -
0.130
P2[4]+P2[6] -
0.133
V
BG - 0.082
2*BG-P2[6] -
0.084
P2[4]-BG -
0.056
P2[4]-P2[6] -
0.057
cc
cc /2+BG - 0.140
cc /2-BG - 0.051
Minimum
/2 - 0.010
V
2*BG - 0.010
P24 0.001
0.000
V
3*BG - 0.018
2*BG+P2[6] -
0.018
P2[4]+BG -
0.016
P2[4]+P2[6] -
0.016
V
BG + 0.023
2*BG-P2[6] +
0.025
P2[4]-BG +
0.026
P24-P26 +
0.026
cc
cc /2+BG - 0.018
cc /2-BG
/2 - 0.004
Typical
+
0.024
DC and AC Characteristics
V
2*BG + 0.024
P24 + 0.014
0.034
V
0.103
3*BG + 0.076
2*BG+P2[6]+
0.077
P2[4]+BG +
0.098
P2[4]+P2[6]+
0.100
V
BG + 0.129
2*BG-P2[6] +
0.134
P2[4]-BG +
0.107
P2[4]-P2[6] +
0.110
cc
cc /2+BG +
cc /2-BG + 0.098
Maximum
/2 + 0.003
Unit
V
V
V
mV
V
V
V
V
V
V
V
V
V
V
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