ZGP323HES2832C Zilog, ZGP323HES2832C Datasheet - Page 55

• Manufacturer Part Number: ZGP323HES2832C
• Description: IC Z8 GP MCU 32K OTP 28SOIC
• Manufacturer: Zilog
• Series: Z8® GP™r

Specifications of ZGP323HES2832C

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: HLVD, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 237 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-3533

PS023807-0707
controls whether a low level or a high level at the XOR-gate input
is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits D2,
D3, and D4 of the SMR register specify the source of the Stop Mode Recovery signal. Bits
D0 determines if SCLK/TCLK are divided by 16 or not. The SMR is located in Bank F of
the Expanded Register Group at address
SCLK/TCLK Divide-by-16 Select (D0)
D0 of the SMR controls a divide-by-16 prescaler of SCLK/TCLK
trol selectively reduces device power consumption during normal processor execution
D7
* Default after Power-On Reset or Watchdog Reset.
* * Default setting after Reset and Stop Mode Recovery.
* * * At the XOR gate input.
* * * * Default setting after reset. Must be 1 if using a crystal or resonator clock source.
SMR(0F)0BH
D6
D5
Figure 31. STOP Mode Recovery Register
D4
D3
D2
D1
D0
0BH
.
SCLK/TCLK Divide-by-16
0 OFF * *
1 ON
Reserved (Must be 0)
Stop Mode Recovery Source
000 POR Only *
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON * * * *
Stop Recovery Level * * *
0 Low *
1 High
Stop Flag
0 POR *
1 Stop Recovery * *
Product Specification
(Figure
(Figure 33
Functional Description
32). This con-
on page 53)
ZGP323H
50