Z8F042AHH020EC Zilog, Z8F042AHH020EC Datasheet - Page 87
![IC ENCORE XP MCU FLASH 4K 20SSOP](/photos/9/30/93032/269-20-ssop_sml.jpg)
Z8F042AHH020EC
Manufacturer Part Number
Z8F042AHH020EC
Description
IC ENCORE XP MCU FLASH 4K 20SSOP
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F042AHH020EC
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3368
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F042AHH020EC2103
Manufacturer:
AVX
Quantity:
25 000
Part Number:
Z8F042AHH020EC2103
Manufacturer:
ZILOG
Quantity:
20 000
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- Download datasheet (4Mb)
PS022825-0908
PWM DUAL OUTPUT Mode
In PWM DUAL OUTPUT mode, the timer outputs a Pulse-Width Modulated (PWM)
output signal pair (basic PWM signal and its complement) through two GPIO Port pins.
The timer input is the system clock. The timer first counts up to the 16-bit PWM match
value stored in the Timer PWM High and Low Byte registers. When the timer count value
matches the PWM value, the Timer Output toggles. The timer continues counting until it
reaches the Reload value stored in the Timer Reload High and Low Byte registers. Upon
reaching the Reload value, the timer generates an interrupt, the count value in the Timer
High and Low Byte registers is reset to
If the TPOL bit in the Timer Control register is set to 1, the Timer Output signal begins as
a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The
Timer Output signal returns to a High (1) after the timer reaches the Reload value and is
reset to
If the TPOL bit in the Timer Control register is set to 0, the Timer Output signal begins as
a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The
Timer Output signal returns to a Low (0) after the timer reaches the Reload value and is
reset to
The timer also generates a second PWM output signal Timer Output Complement. The
Timer Output Complement is the complement of the Timer Output PWM signal. A
programmable deadband delay can be configured to time delay (0 to 128 system clock
cycles) PWM output transitions on these two pins from a low to a high (inactive to active).
This ensures a time gap between the deassertion of one PWM output to the assertion of its
complement.
Follow the steps below for configuring a timer for PWM DUAL OUTPUT mode and initi-
ating the PWM operation:
1. Write to the Timer Control register to:
2. Write to the Timer High and Low Byte registers to set the starting count value
3. Write to the PWM High and Low Byte registers to set the PWM value.
4. Write to the PWM Control register to set the PWM dead band delay value. The
–
–
–
–
(typically
reset in PWM mode, counting always begins at the reset value of
deadband delay must be less than the duration of the positive phase of the PWM signal
(as defined by the PWM high and low byte registers). It must also be less than the
0001H
0001H
Disable the timer.
Configure the timer for PWM DUAL OUTPUT mode by writing the TMODE bits
in the TxCTL1 register and the TMODEHI bit in TxCTL0 register.
Set the prescale value.
Set the initial logic level (High or Low) and PWM High/Low transition for the
Timer Output alternate function.
0001H
.
.
). This only affects the first pass in PWM mode. After the first timer
0001H
and counting resumes.
Z8 Encore! XP
Product Specification
0001H
®
F082A Series
.
Timers
76
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