Z8F3201VN020SC00TR Zilog, Z8F3201VN020SC00TR Datasheet - Page 167

IC ENCORE MCU FLASH 32K 44PLCC

Z8F3201VN020SC00TR

Manufacturer Part Number
Z8F3201VN020SC00TR
Description
IC ENCORE MCU FLASH 32K 44PLCC
Manufacturer
Zilog
Series
Encore!®r
Datasheet

Specifications of Z8F3201VN020SC00TR

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
Z8F3201VN020SC00T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z8F3201VN020SC00TR
Manufacturer:
Zilog
Quantity:
10 000
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
®
Z8 Encore!
149
Program Memory Address 0000H
Table 90. Option Bits At Program Memory Address 0000H
BITS
7
6
5
4
3
2
1
0
WDT_RES WDT_AO
Reserved
RP
FHSWP
FWP
FIELD
U
U
U
U
U
U
U
U
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Program Memory 0000H
ADDR
Note: U = Unchanged by Reset. R/W = Read/Write.
WDT_RES—Watch-Dog Timer Reset
0 = Watch-Dog Timer time-out generates an interrupt request. Interrupts must be globally
enabled for the eZ8 CPU to acknowledge the interrupt request.
1 = Watch-Dog Timer time-out causes a Short Reset. This setting is the default for unpro-
grammed (erased) Flash.
WDT_AO—Watch-Dog Timer Always On
0 = Watch-Dog Timer is automatically enabled upon application of system power. Watch-
Dog Timer can not be disabled.
1 = Watch-Dog Timer is enabled upon execution of the WDT instruction. Once enabled,
the Watch-Dog Timer can only be disabled by a Reset or Stop Mode Recovery. This set-
ting is the default for unprogrammed (erased) Flash.
Reserved
These Option Bits are reserved for future use and must always be set to 1. This setting is
the default for unprogrammed (erased) Flash.
RP—Read Protect
0 = User program code is inaccessible. Limited control features are available through the
On-Chip Debugger.
1 = User program code is accessible. All On-Chip Debugger commands are enabled. This
setting is the default for unprogrammed (erased) Flash.
PS017610-0404
Option Bits

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