CY8C26643-24AI Cypress Semiconductor Corp, CY8C26643-24AI Datasheet - Page 31

• Manufacturer Part Number: CY8C26643-24AI
• Description: IC MCU 16K FLASH 256B 44LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ CY8C26xxxr

Specifications of CY8C26643-24AI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.25 V
• Data Converters: A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 428-1431; 428-1431-5; 428-1431

6.0
6.1
Table 28:
Port 0 Data Register (PRT0DR, Address = Bank 0, 00h)
Port 1 Data Register (PRT1DR, Address = Bank 0, 04h)
Port 2 Data Register (PRT2DR, Address = Bank 0, 08h)
Port 3 Data Register (PRT3DR, Address = Bank 0, 0Ch)
Port 4 Data Register (PRT4DR, Address = Bank 0, 10h)
Port 5 Data Register (PRT5DR, Address = Bank 0, 14h) Note : Port 5 is 4-bits wide, Bit [3:0]
6.2
Table 29:
Port 0 Interrupt Enable Register (PRT0IE, Address = Bank 0, 01h)
Port 1 Interrupt Enable Register (PRT1IE, Address = Bank 0, 05h)
Port 2 Interrupt Enable Register (PRT2IE, Address = Bank 0, 09h)
Port 3 Interrupt Enable Register (PRT3IE, Address = Bank 0, 0Dh)
Port 4 Interrupt Enable Register (PRT4IE, Address = Bank 0, 11h)
Port 5 Interrupt Enable Register (PRT5IE, Address = Bank 0, 15h) Note : Port 5 is 4-bits wide
September 5, 2002
Bit [7:0] : Data [7:0] When written is the bits for output on port pins. When read is the state of the port pins
Bit [7:0] : Int En [7:0] When written sets the pin interrupt state
0 = Interrupt disabled for pin
1 = Interrupt enabled for pin
Read/Write
Read/Write
Bit Name
Bit Name
Bit #
POR
Bit #
POR
I/O Registers
Port Data Registers
Port Interrupt Enable Registers
Port Data Registers
Port Interrupt Enable Registers
Data [7]
Int En [7]
RW
7
0
W
7
0
Data [6]
Int En [6]
RW
6
0
W
6
0
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
Data [5]
Int En [5] Int En [4]
RW
5
0
W
5
0
Data [4]
RW
W
4
0
4
0
Int En [3]
Data [3]
RW
W
3
0
3
0
Int En [2]
Data [2]
RW
W
2
0
2
0
Int En [1]
Data [1]
RW
W
1
0
1
0
I/O Registers
Int En [0]
Data [0]
RW
W
0
0
0
0
31