EP7311-CB-90 Cirrus Logic Inc, EP7311-CB-90 Datasheet - Page 24

• Manufacturer Part Number: EP7311-CB-90
• Description: IC ARM720T MCU 90MHZ 256-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP7r

Specifications of EP7311-CB-90

• Core Processor: ARM7
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: Codec, EBI/EMI, IrDA, Keypad, Multimedia Codec, SPI/Microwire1, UART/USART
• Peripherals: LCD, LED, MaverickKey, PWM
• Number Of I /o: 27
• Program Memory Type: ROMless
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 2.7 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: 598-1221

EP7311
High-Performance, Low-Power System on Chip
Static Memory Burst Read Cycle
24
EXPRDY
EXPCLK
WRITE
WORD
WORD
nMWE
nMOE
HALF
nCS
A
D
Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to
determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion
cycles. This improves performance so the SQAEN bit should always be set where possible.
4. Address, Halfword, Word, and Write hold state until next cycle.
t
CSd
t
Ad
t
WRd
t
MOEd
t
t
HWd
WDd
t
Figure 9. Static Memory Burst Read Cycle Timing Measurement
EXs
©
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EXh
Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
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