AT91SAM7S32-AU-999 Atmel, AT91SAM7S32-AU-999 Datasheet
AT91SAM7S32-AU-999
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AT91SAM7S32-AU-999 Summary of contents
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... Kbytes (AT91SAM7S128) Organized in 512 Pages of 256 Bytes (Single Plane) – 64 Kbytes (AT91SAM7S64) Organized in 512 Pages of 128 Bytes (Single Plane) – 32 Kbytes (AT91SAM7S321/32) Organized in 256 Pages of 128 Bytes (Single Plane) – 16 Kbytes (AT91SAM7S161/16) Organized in 256 Pages of 64 Bytes (Single Plane) – ...
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... One Three-channel 16-bit Timer/Counter (TC) – Three External Clock Input and Two Multi-purpose I/O Pins per Channel (AT91SAM7S512/256/128/64/321/161) – One External Clock Input and Two Multi-purpose I/O Pins for the first Two Channels Only (AT91SAM7S32/16) – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability • ...
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... Atmel’s AT91SAM7S is a series of low pincount Flash microcontrollers based on the 32-bit ARM RISC processor. It features a high-speed Flash and an SRAM, a large set of peripherals, includ- ing a USB 2.0 device (except for the AT91SAM7S32 and AT91SAM7S16), and a complete set of system functions minimizing the number of external components. The device is an ideal migration path for 8-bit microcontroller users looking for additional performance and extended memory ...
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Block Diagram Figure 2-1. AT91SAM7S512/256/128/64/321/161 Block Diagram TDI TDO JTAG TMS SCAN TCK JTAGSEL System Controller TST FIQ IRQ0-IRQ1 PCK0-PCK2 PLLRC PLL XIN OSC XOUT RCOSC VDDCORE BOD POR VDDCORE NRST DRXD DTXD RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 ...
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... Figure 2-2. AT91SAM7S32/16 Block Diagram TDI TDO TMS TCK JTAGSEL System Controller TST FIQ IRQ0 PCK0-PCK2 PLLRC PLL XIN OSC XOUT VDDCORE BOD POR VDDCORE NRST DRXD DTXD RXD0 TXD0 SCK0 RTS0 CTS0 NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK ADTRG ...
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... No pull-up resistor No pull-up resistor No pull-up resistor (1) Pull-down resistor (1) Pull-down resistor Open-drain with pull-Up resistor (1) Pull-down resistor IRQ1 not present on AT91SAM7S32/16 Pulled-up input at reset PA0 - PA20 only on AT91SAM7S32/16 6175IS–ATARM–30-Aug-10 ...
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... Comments not present on AT91SAM7S32/16 not present on AT91SAM7S32/16 SCK1 not present on AT91SAM7S32/16 TXD1 not present on AT91SAM7S32/16 RXD1 not present on AT91SAM7S32/16 RTS1 not present on AT91SAM7S32/16 CTS1 not present on AT91SAM7S32/16 not present on AT91SAM7S32/16 not present on AT91SAM7S32/16 not present on AT91SAM7S32/16 not present on AT91SAM7S32/16 TCLK1 and TCLK2 not present on ...
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... Type Level Two-Wire Interface I/O I/O Analog-to-Digital Converter Analog Analog Input Analog Fast Flash Programming Interface Input Input I/O Output High Output Low Input Low Input Input Low 14. Comments Digital pulled-up inputs at reset Analog Inputs PGMD0-PGMD7 only on AT91SAM7S32/16 6175IS–ATARM–30-Aug-10 ...
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... Package and Pinout The AT91SAM7S512/256/128/64/321 are available in a 64-lead LQFP or 64-pad QFN package. The AT91SAM7S161 is available in a 64-Lead LQFP package. The AT91SAM7S32/16 are available in a 48-lead LQFP or 48-pad QFN package. 4.1 64-lead LQFP and 64-pad QFN Package Outlines Figure 4-1 age. A detailed mechanical description is given in the section Mechanical Characteristics of the full datasheet ...
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LQFP and 64-pad QFN Pinout Table 4-1. AT91SAM7S512/256/128/64/321/161 Pinout 1 ADVREF 17 2 GND 18 3 AD4 19 4 AD5 20 5 AD6 21 6 AD7 22 7 VDDIN 23 8 VDDOUT 24 9 PA17/PGMD5/AD0 25 10 PA18/PGMD6/AD1 ...
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... LQFP and 48-pad QFN Package Outlines Figure 4-3 age. A detailed mechanical description is given in the section Mechanical Characteristics of the full datasheet. Figure 4-3. Figure 4-4. 4.4 48-lead LQFP and 48-pad QFN Pinout Table 4-2. AT91SAM7S32/16 Pinout 1 ADVREF 13 2 GND 14 3 AD4 ...
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Power Considerations 5.1 Power Supplies The AT91SAM7S Series has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: • VDDIN ...
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Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 ...
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... PIO Controller A Lines • All the I/O lines PA0 to PA31on AT91SAM7S512/256/128/64/321 (PA0 to PA20 on AT91SAM7S32) are 5V-tolerant and all integrate a programmable pull-up resistor. • All the I/O lines PA0 to PA31 on AT91SAM7S161 (PA0 to PA20 on AT91SAM7S16) are not 5V-tolerant and all integrate a programmable pull-up resistor. ...
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... The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive permanently. The remaining I/O lines can draw only 8 mA. However, the total current drawn by all the I/O lines cannot exceed 150 mA (100 mA for AT91SAM7S32/16). 6175IS–ATARM–30-Aug-10 AT91SAM7S Series Summary 15 ...
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Processor and Architecture 7.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture – Runs MHz, providing 0.9 MIPS/MHz • Two instruction sets – ARM – Thumb • Three-stage pipeline architecture – Instruction ...
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... Peripheral DMA Controller • Handles data transfer between peripherals and memories • Eleven channels: AT91SAM7S512/256/128/64/321/161 • Nine channels: AT91SAM7S32/16 – Two for each USART – Two for the Debug Unit – Two for the Serial Synchronous Controller – Two for the Serial Peripheral Interface – ...
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Memories 8.1 AT91SAM7S512 • 512 Kbytes of Flash Memory, dual plane – 2 contiguous banks of 1024 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, ...
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... Protection Mode to secure contents of the Flash • 16 Kbytes of Fast SRAM – Single-cycle access at full speed 8.5 AT91SAM7S321/32 • 32 Kbytes of Flash Memory, single plane – 256 pages of 128 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – ...
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... BFFF 0xFFFB C000 Reserved 0xFFFB FFFF 0xFFFC 0000 USART0 16 Kbytes 0xFFFC 3FFF 16 Kbytes 0xFFFC 4000 USART1 (Reserved on 0xFFFC 7FFF AT91SAM7S32/16) 0xFFFC 8000 Reserved 0xFFFC BFFF 0xFFFC C000 PWMC 16 Kbytes 0xFFFC FFFF 0xFFFD 0000 Reserved 0xFFFD 3FFF 0xFFFD 4000 SSC 16 Kbytes ...
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... The AT91SAM7S128 features one bank (single plane) of 128 Kbytes of Flash. • The AT91SAM7S64 features one bank (single plane Kbytes of Flash. • The AT91SAM7S321/32 features one bank (single plane Kbytes of Flash. • The AT91SAM7S161/16 features one bank (single plane Kbytes of Flash. ...
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... The Flash of the AT91SAM7S64 is organized in 512 pages (single plane) of 128 bytes. The 65,536 bytes are organized in 32-bit words. • The Flash of the AT91SAM7S321/32 is organized in 256 pages (single plane) of 128 bytes. The 32,768 bytes are organized in 32-bit words. • The Flash of the AT91SAM7S161/16 is organized in 256 pages (single plane bytes. ...
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Lock Regions 8.8.3.1 AT91SAM7S512 Two Embedded Flash Controllers each manage 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7S512 contains 32 lock regions and each lock region contains 64 ...
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... AT91SAM7S321/32 The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7S321/32 contains 8 lock regions and each lock region contains 32 pages of 128 bytes. Each lock region has a size of 4 Kbytes locked-region’s erase or program command occurs, the command is aborted and the LOCKE bit in the MC_FSR register rises and the interrupt line rises if the LOCKE bit has been written the MC_FMR register ...
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Security Bit Feature The AT91SAM7S Series features a security bit, based on a specific NVM Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is ...
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... The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program in situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication through the DBGU or through the USB Device Port. (The AT91SAM7S32/16 have no USB Device Port.) • Communication through the DBGU supports a wide range of crystals from MHz via software auto-detection. ...
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Figure 9-1. System Controller Block Diagram (AT91SAM7S512/256/128/64/321/161) NRST XIN XOUT PLLRC PA0-PA31 6175IS–ATARM–30-Aug-10 AT91SAM7S Series Summary wdt_irq dbgu_irq pmc_irq rstc_irq MCK Debug periph_nreset Unit dbgu_rxd Periodic MCK debug Interval periph_nreset Timer SLCK Real-Time Timer periph_nreset SLCK Watchdog debug idle Timer ...
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... Figure 9-2. System Controller Block Diagram (AT91SAM7S32/16) periph_irq[2..14] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset periph_nreset en BOD POR NRST RCOSC XIN OSC XOUT PLL PLLRC periph_nreset periph_nreset periph_clk[2] PA0-PA20 AT91SAM7S Series Summary 28 Interrupt Controller MCK Debug Unit dbgu_rxd Periodic MCK ...
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Reset Controller The Reset Controller is based on a power-on reset cell and one brownout detector. It gives the status of the last reset, indicating whether power-up reset, a software reset, a user reset, a watchdog ...
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... The Power Management Controller uses the Clock Generator outputs to provide: • the Processor Clock PCK • the Master Clock MCK • the USB Clock UDPCK (not present on AT91SAM7S32/16) • all the peripheral clocks, independently controllable • three programmable clock outputs The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating fre- quency of the device ...
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Figure 9-4. 9.4 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ ARM Processor • Individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is ...
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... Chip ID is 0x27090544 for AT91SAM7S64 Rev C – Chip ID is 0x27080342 for AT91SAM7S321 Rev A – Chip ID is 0x27080340 for AT91SAM7S32 Rev A – Chip ID is 0x27080341 for AT91SAM7S32 Rev B – Chip ID is 0x27050241 for AT9SAM7S161 Rev A – Chip ID is 0x27050240 for AT91SAM7S16 Rev A Note: 9 ...
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... Programmable 16-bit prescaler for SLCK accuracy compensation 9.9 PIO Controller • One PIO Controller, controlling 32 I/O lines (21 for AT91SAM7S32/16) • Fully programmable through set/clear registers • Multiplexing of two peripheral functions per I/O line • For each I/O line (whether assigned to a peripheral or used as general-purpose I/O) – ...
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... Peripheral Identifiers The AT91SAM7S Series embeds a wide range of peripherals. Identifiers of the AT91SAM7S512/256/128/64/321/161. fiers of the AT91SAM7S32/16. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. ...
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... The AT91SAM7S Series features one PIO controller, PIOA, that multiplexes the I/O lines of the peripheral set. PIO Controller A controls 32 lines (21 lines for AT91SAM7S32/16). Each line can be assigned to one of two peripheral functions Some of them can also be multiplexed with the analog inputs of the ADC Controller. ...
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PIO Controller A Multiplexing Table 10-3. Multiplexing on PIO Controller A (AT91SAM7S512/256/128/64/321/161) PIO Controller A I/O Line Peripheral A PA0 PWM0 PA1 PWM1 PA2 PWM2 PA3 TWD PA4 TWCK PA5 RXD0 PA6 TXD0 PA7 RTS0 PA8 CTS0 PA9 DRXD ...
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... Table 10-4. Multiplexing on PIO Controller A (AT91SAM7S32/16) PIO Controller A I/O Line Peripheral A PA0 PWM0 PA1 PWM1 PA2 PWM2 PA3 TWD PA4 TWCK PA5 RXD0 PA6 TXD0 PA7 RTS0 PA8 CTS0 PA9 DRXD PA10 DTXD PA11 NPCS0 PA12 MISO PA13 MOSI PA14 SPCK ...
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... Receiver time-out and transmitter timeguard – Multi-drop Mode with address generation and detection • RS485 with driver control signal AT91SAM7S Series Summary 38 peripherals Sensors and data per chip select 2 compatible devices (refer to the TWI sections of the datasheet AT91SAM7S32/16) ® and 3-wire EEPROMs 6175IS–ATARM–30-Aug-10 ...
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... Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 10.9 Timer Counter • Three 16-bit Timer Counter Channels – Two output compare or one input capture per channel (except for AT91SAM7S32/16 • Wide range of functions including: – Frequency measurement – Event counting – Interval measurement – ...
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... Independent period and duty cycle, with double buffering – Programmable selection of the output waveform polarity – Programmable center or left aligned output waveform 10.11 USB Device Port (Does not pertain to AT91SAM7S32/16) • USB V2.0 full-speed compliant, 12 Mbits per second. • Embedded USB V2.0 full-speed transceiver • ...
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Package Drawings The SAM7S series devices are available in LQFP and QFN package types. 11.1 LQFP Packages Figure 11-1. 48-and 64-lead LQFP Package Drawing 6175IS–ATARM–30-Aug-10 AT91SAM7S Series Summary 41 ...
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Table 11-1. Symbol θ 1 θ 2 θ aaa bbb ccc ddd AT91SAM7S Series Summary 42 48-lead LQFP Package Dimensions (in ...
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Table 11-2. Symbol θ θ θ aaa bbb ccc ddd 6175IS–ATARM–30-Aug-10 AT91SAM7S Series Summary 64-lead LQFP Package Dimensions (in mm) Millimeter Min ...
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QFN Packages Figure 11-2. 48-pad QFN Package AT91SAM7S Series Summary 44 6175IS–ATARM–30-Aug-10 ...
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Table 11-3. Symbol aaa bbb ccc 6175IS–ATARM–30-Aug-10 AT91SAM7S Series Summary 48-pad QFN Package Dimensions (in mm) Millimeter Min Nom Max – – 090 – – 0.050 – 0.65 ...
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Figure 11-3. 64-pad QFN Package Drawing ll dimensions are in mm eference : JEDEC Drawing MO-220 AT91SAM7S Series Summary 46 6175IS–ATARM–30-Aug-10 ...
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Table 11-4. Symbol aaa bbb ccc 6175IS–ATARM–30-Aug-10 AT91SAM7S Series Summary 64-pad QFN Package Dimensions (in mm) Millimeter Min Nom Max – – 090 – – 0.05 – 0.65 ...
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... AT91SAM7S Ordering Information Table 12-1. AT91SAM7S Series Ordering Information MLR A Ordering Code MLR B Ordering Code AT91SAM7S16-AU AT91SAM7S16-MU AT91SAM7S161-AU AT91SAM7S32-AU-001 AT91SAM7S32B-AU AT91SAM7S32-MU AT91SAM7S32B-MU AT91SAM7S321-AU AT91SAM7S321-MU AT91SAM7S64B-AU – AT91SAM7S64B-MU AT91SAM7S128-AU-001 – AT91SAM7S128-MU AT91SAM7S256-AU-001 – AT91SAM7S256-MU AT91SAM7S512-AU AT91SAM7S512B-AU AT91SAM7S512-MU AT91SAM7S512B-MU AT91SAM7S Series Summary 48 MLR C Ordering Code – ...
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... SYSIRQ changed to SYSC in “Peripheral Identifiers” 6175FS AT91SAM7S161 and AT91SAM7S16 added to product family Features: Timer Counter, on Summary,” on page 3, footnote explains TC on AT91SAM7S32/16 has only two channels accessible via PIO, and in Section 10.9 ”Timer Section 10.6 ”Two-wire slave addressing, Modes for AT91SAM7S161/16 “ ...
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Doc. Rev Comments 6175GS “Features”,“Debug Unit (DBGU)” Communication” Section 7.4 ”Peripheral DMA Section 9. ”System Controller”, Section 9.1.1 ”Brownout Detector and Power-on Section 9.5 ”Debug Unit”, the list; B and SAM7S64 Rev B to the list. Section 12. ”AT91SAM7S Ordering ...
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