ATMEGA324P-15AZ Atmel, ATMEGA324P-15AZ Datasheet - Page 193
ATMEGA324P-15AZ
Manufacturer Part Number
ATMEGA324P-15AZ
Description
MCU AVR 32K FLASH 15MHZ 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA324P-15AZ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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7674F–AVR–09/09
Table 17-4.
Note:
• Bits 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPMn setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
Table 17-5.
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Table 17-6.
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
Table 17-7.
UMSELn1
UCSZn2
UPMn1
1. See
0
0
0
0
1
0
0
1
1
0
1
1
operation
UMSELn Bits Settings
UPMn Bits Settings
USBS Bit Settings
UCSZn Bits Settings
USBSn
“USART in SPI Mode” on page 199
0
1
UCSZn1
UMSELn0
UPMn0
0
0
1
1
0
0
1
0
1
1
0
1
Stop Bit(s)
1-bit
2-bit
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
Mode
Synchronous USART
(Reserved)
Master SPI (MSPIM)
UCSZn0
for full description of the Master SPI Mode (MSPIM)
ATmega164P/324P/644P
0
1
0
1
0
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
(1)
193
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