ATMEGA1284P-MU Atmel, ATMEGA1284P-MU Datasheet - Page 47
![MCU AVR 128K ISP FLASH 44-QFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA1284P-MU
Manufacturer Part Number
ATMEGA1284P-MU
Description
MCU AVR 128K ISP FLASH 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA644PA-PU.pdf
(581 pages)
2.ATMEGA644PA-PU.pdf
(32 pages)
3.ATMEGA1284P-MU.pdf
(20 pages)
Specifications of ATMEGA1284P-MU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
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Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
PEREGRIN
Quantity:
1 992
Part Number:
ATMEGA1284P-MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
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Manufacturer:
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Quantity:
593
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- Download datasheet (27Mb)
9.11.5
9.11.6
9.11.7
8272A–AVR–01/10
Watchdog Timer
Port Pins
On-chip Debug System
If the Watchdog Timer is not needed in the application, the module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consump-
tion. Refer to
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important is then to ensure that no pins drive resistive loads. In sleep modes where both
the I/O clock (clk
be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section
which pins are enabled. If the input buffer is enabled and the input signal is left floating or have
an analog signal level close to V
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and
DIDR0). Refer to
Input Disable Register 0” on page 260
If the On-chip debug system is enabled by the OCDEN Fuse and the chip enters sleep mode,
the main clock source is enabled, and hence, always consumes power. In the deeper sleep
modes, this will contribute significantly to the total current consumption.
There are three alternative ways to disable the OCD system:
• Disable the OCDEN Fuse.
• Disable the JTAGEN Fuse.
• Write one to the JTD bit in MCUCR.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
”Interrupts” on page 62
CC
I/O
”DIDR1 – Digital Input Disable Register 1” on page 240
/2 on an input pin can cause significant current even in active mode. Digital
) and the ADC clock (clk
”Digital Input Enable and Sleep Modes” on page 77
CC
/2, the input buffer will use excessive power.
for details on how to configure the Watchdog Timer.
for details.
ADC
) are stopped, the input buffers of the device will
and
”DIDR0 – Digital
for details on
47
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