ATMEGA88PA-PU Atmel, ATMEGA88PA-PU Datasheet - Page 272
![MCU AVR 8K ISP FLASH MEM 28-DIP](/photos/7/21/72189/453-28-dip_sml.jpg)
ATMEGA88PA-PU
Manufacturer Part Number
ATMEGA88PA-PU
Description
MCU AVR 8K ISP FLASH MEM 28-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA48A-PU.pdf
(566 pages)
2.ATMEGA48A-PU.pdf
(33 pages)
3.ATMEGA48PA-MMH.pdf
(26 pages)
Specifications of ATMEGA88PA-PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATASTK512-EK1-IND
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Package
28PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA88PA-PU
Manufacturer:
MICREL
Quantity:
2 001
Company:
Part Number:
ATMEGA88PA-PU
Manufacturer:
Atmel
Quantity:
27 830
- Current page: 272 of 566
- Download datasheet (23Mb)
25.2.1
25.2.2
8271C–AVR–08/10
EEPROM Write Prevents Writing to SPMCSR
Reading the Fuse and Lock Bits from Software
Figure 25-1. Addressing the Flash During SPM
Note:
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM
instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are set
in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET
and SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM
instruction is executed within three CPU cycles or no SPM instruction is executed within four
CPU cycles. When BLBSET and SELFPRGEN are cleared, LPM will work as described in the
Instruction set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET
and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles
after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low byte
(FLB) will be loaded in the destination register as shown below.See
a detailed description and mapping of the Fuse Low byte.
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Bit
Rd
Bit
Rd
Z - REGISTER
1. The different variables used in
PROGRAM MEMORY
BIT
PAGE
PROGRAM
COUNTER
15
FLB7
7
7
–
PAGE ADDRESS
WITHIN THE FLASH
ZPCMSB
PCMSB
FLB6
6
6
–
PCPAGE
FLB5
5
5
–
Figure 26-3
ZPAGEMSB
PAGEMSB
FLB4
PCWORD
4
–
4
WORD ADDRESS
WITHIN A PAGE
(1)
are listed in
1
FLB3
0
0
3
–
3
INSTRUCTION WORD
PAGE
Table 27-11 on page
FLB2
2
–
2
Table 27-5 on page 298
FLB1
LB2
1
1
PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
FLB0
301.
LB1
0
0
272
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