ATMEGA88P-20MU Atmel, ATMEGA88P-20MU Datasheet - Page 228
![MCU AVR 8K ISP FLASH 20MHZ 32QFN](/photos/12/43/124398/atmega88p-20mu_sml.jpg)
ATMEGA88P-20MU
Manufacturer Part Number
ATMEGA88P-20MU
Description
MCU AVR 8K ISP FLASH 20MHZ 32QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA88P-20MU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATASTK512-EK1-IND
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
32MLF
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
For Use With
ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA88P-20MU
Manufacturer:
ATMEL
Quantity:
12 246
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21.7.2
8025L–AVR–7/10
Master Receiver Mode
Figure 21-12. Formats and States in the Master Transmitter Mode
In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter
(Slave see
ted. The format of the following address packet determines whether Master Transmitter or
Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R
is transmitted, MR mode is entered. All the status codes mentioned in this section assume that
the prescaler bits are zero or are masked to zero.
Successfull
transmission
to a slave
receiver
Next transfer
started with a
repeated start
condition
Not acknowledge
received after the
slave address
Not acknowledge
received after a data
byte
Arbitration lost in slave
address or data byte
Arbitration lost and
addressed as slave
Figure
From master to slave
From slave to master
$08
S
21-13). In order to enter a Master mode, a START condition must be transmit-
SLA
W
MT
A or A
DATA
$18
$20
$38
$68
A
A
A
$78
Other master
Other master
n
continues
continues
P
$B0
DATA
A
ATmega48P/88P/168P
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the 2-Wire Serial Bus. The
prescaler bits are zero or masked to zero
A or A
$28
$30
$38
To corresponding
states in slave mode
A
A
Other master
$10
continues
P
R
P
S
SLA
W
R
MR
228
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