AT89C51SND1C-7HTUL Atmel, AT89C51SND1C-7HTUL Datasheet - Page 167

• Manufacturer Part Number: AT89C51SND1C-7HTUL
• Description: IC MCU 64KB FLASH MEM 81-CBGA
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51SND1C-7HTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 81-CBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 137. Status for Master Transmitter Mode
4109L–8051–02/08
SSSTA
Status
Code
08h
10h
18h
20h
28h
30h
38h
Status of the TWI Bus
and TWI Hardware
A START condition has
been transmitted
A repeated START
condition has been
transmitted
SLA+W has been
transmitted; ACK has
been received
SLA+W has been
transmitted; NOT ACK
has been received
Data Byte has been
transmitted; ACK has
been received
Data Byte has been
transmitted; NOT ACK
has been received
Arbitration lost in
SLA+W or data Bytes
To/From SSDAT
Write SLA+W
Write SLA+W
Write SLA+R
Write data Byte
No SSDAT action
No SSDAT action
No SSDAT action
Write data Byte
No SSDAT action
No SSDAT action
No SSDAT action
Write data Byte
No SSDAT action
No SSDAT action
No SSDAT action
Write data Byte
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
Application Software Response
SSSTA
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SSSTO
To SSCON
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
SSI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSAA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Next Action Taken by TWI Hardware
SLA+W will be transmitted.
SLA+W will be transmitted.
SLA+R will be transmitted.
Logic will switch to master receiver mode
Data Byte will be transmitted.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Data Byte will be transmitted.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Data Byte will be transmitted.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Data Byte will be transmitted.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
TWI bus will be released and not addressed slave
mode will be entered.
A START condition will be transmitted when the bus
becomes free.
AT8xC51SND1C
167