AT91SAM7S64-MU Atmel, AT91SAM7S64-MU Datasheet - Page 539
AT91SAM7S64-MU
Manufacturer Part Number
AT91SAM7S64-MU
Description
IC ARM7 MCU FLASH 64K 64QFN
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7S64-MU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN
For Use With
AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Figure 36-3. GOVRE and OVREx Flag Behavior
6175K–ATARM–30-Aug-10
(ADC_CHSR)
(ADC_CHSR)
ADC_LCDR
ADC_CDR0
ADC_CDR1
(ADC_SR)
(ADC_SR)
(ADC_SR)
(ADC_SR)
(ADC_SR)
GOVRE
ADTRG
DRDY
OVRE0
EOC0
EOC1
CH0
CH1
Undefined Data
Undefined Data
If the ADC_CDR is not read before further incoming data is converted, the corresponding Over-
run Error (OVRE) flag is set in the Status Register (ADC_SR).
In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun
Error) in ADC_SR.
The OVRE and GOVRE flags are automatically cleared when ADC_SR is read.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled and
then reenabled during a conversion, its associated data and its corresponding EOC and OVRE
flags in ADC_SR are unpredictable.
Conversion
Undefined Data
Conversion
Data A
AT91SAM7S Series Preliminary
Data A
Data B
Conversion
Data B
Data C
Read ADC_CDR1
Data C
Read ADC_CDR0
Read ADC_SR
539
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