ATMEGA6490-16AI Atmel, ATMEGA6490-16AI Datasheet - Page 194
ATMEGA6490-16AI
Manufacturer Part Number
ATMEGA6490-16AI
Description
IC AVR MCU FLASH 64K 5V 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA329-16AU.pdf
(392 pages)
Specifications of ATMEGA6490-16AI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
For Use With
ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATSTK504 - STARTER KIT AVR EXP MOD 100P LCD
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA6490-16AI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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19.11.5
194
ATmega329/3290/649/6490
UBRRnL and UBRRnH – USART Baud Rate Registers n
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCK).
Table 19-12. UCPOLn Bit Settings
• Bit 15:12 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit must be
written to zero when UBRRnH is written.
• Bit 11:0 – UBRR11:0: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRnH contains the four
most significant bits, and the UBRRnL contains the eight least significant bits of the USART
baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud
rate is changed. Writing UBRRnL will trigger an immediate update of the baud rate prescaler.
Bit
Read/Write
Initial Value
UCPOLn
0
1
R/W
15
R
–
7
0
0
R/W
14
R
–
6
0
0
Transmitted Data Changed
(Output of TxD Pin)
Rising XCK Edge
Falling XCK Edge
R/W
13
R
–
5
0
0
R/W
12
R
–
4
0
0
UBRRn[7:0]
R/W
R/W
11
3
0
0
R/W
R/W
10
UBRRn[11:8]
2
0
0
Received Data Sampled
(Input on RxD Pin)
Falling XCK Edge
Rising XCK Edge
R/W
R/W
9
1
0
0
R/W
R/W
0
0
0
8
UBRRnH
UBRRnL
2552K–AVR–04/11
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