AT91M43300-25CJ Atmel, AT91M43300-25CJ Datasheet - Page 17

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AT91M43300-25CJ

Manufacturer Part Number
AT91M43300-25CJ
Description
IC ARM7 MCU 144 BGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet

Specifications of AT91M43300-25CJ

Core Processor
ARM7
Core Size
16/32-Bit
Speed
25MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
WDT
Number Of I /o
58
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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Figure 18-3.
Note: 1.
1322B–ATARM–12-Dec-05
MCKI
NWAIT
NRD
These numbers refer to the standard access cycles.
Number of Standard Wait States is One
1 (1)
If the first two conditions are not met during a 32-bit read access, the first 16-bit data is read at
the end of the standard 16-bit read access. In the following example, the number of standard
waits is one. NWAIT assertions do affect both NRD pulse lengths, but first data sampling is not
delayed. The second data sampling is correct.
If the first two conditions are not met during write accesses, the NWE signal is not affected by
the NWAIT assertion. The following example illustrates the number of standard wait states.
NWAIT is not asserted during the first cycle, but is asserted at the second and last cycle of the
standard access. The access is correctly delayed as the NCS line rises accordingly to the
NWAIT assertion. However, the NWE signal waveform is unchanged, and rises too early.
EB16
32-bit Access = Two 16-bit Accesses
Each Access Length = One Wait State + Assertion for One More Cycle
2 (1)
First Data Sampling
(Erroneous)
2 (1)
1 (1)
2 (1)
AT91M43300
2 (1)
Second Data
Sampling
(Correct)
17

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