AT87C51RC2-3CSUL Atmel, AT87C51RC2-3CSUL Datasheet - Page 27

• Manufacturer Part Number: AT87C51RC2-3CSUL
• Description: IC 8051 MCU 32K OTP 30MHZ 40DIP
• Manufacturer: Atmel
• Series: 87Cr

Specifications of AT87C51RC2-3CSUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 30/20MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: UART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Figure 6-5.
4188F–8051–01/08
PCA Timer/Counter
PCA Interrupt System
Module 0
Module 1
Module 2
Module 3
Module 4
CMOD.0
PCA Modules: each one of the five compare/capture modules has six possible functions. It can
perform:
In addition, module 4 can be used as a Watchdog Timer.
Each module in the PCA has a special function register associated with it. These registers are:
CCAPM0 for module 0, CCAPM1 for module 1, etc. (See Table 6-6). The registers contain the
bits that control the mode that each module will operate in.
• 16-bit Capture, positive-edge triggered,
• 16-bit Capture, negative-edge triggered,
• 16-bit Capture, both positive and negative-edge triggered,
• 16-bit Software Timer,
• 16-bit High Speed Output,
• 8-bit Pulse Width Modulator.
• The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the
• PWM (CCAPMn.1) enables the pulse width modulation mode.
• The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to
• The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be
• The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a
CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the
associated module.
toggle when there is a match between the PCA counter and the module's capture/compare
register.
set when there is a match between the PCA counter and the module's capture/compare
register.
capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit
enables the positive edge. If both bits are set both edges will be enabled and a capture will
occur for either transition.
ECF
CF
ECCFn CCAPMn.0
CR
CCF4 CCF3 CCF2 CCF1 CCF0
IE.6
EC
IE.7
EA
AT/TS8xC51Rx2
priority decoder
CCON
0xD8
To Interrupt
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